Quectel M50, Hardware Design

Page: 21 / 89

M50 Hardware Design
M50_HD_V2.0 - 21 -
Table 5: M50 pin assignment
管脚号 管脚名 输入
/
输出 管脚号 管脚名 输入
/
输出
1 ADC1 I 2 ADC0 I
3 RESERVED 4 NETLIGHT O
5 SPK2P O 6 AGND
7 MIC2P I 8 MIC2N I
9 MIC1P I 10 MIC1N I
11 SPK1N O 12 SPK1P O
13 LOUDSPKN O 14 LOUDSPKP O
15 STATUS O 16 PWRKEY I
17 EMERG_OFF I 18 PCM_IN I
19 PCM_CLK O 20 PCM_OUT O
21 PCM_SYNC O 22 RESERVED
23 RESERVED 24 RESERVED
25 RESERVED 26 RESERVED
27 RESERVED 28 RESERVED
29 RESERVED 30 RESERVED
31 RESERVED 32 RESERVED
33 RESERVED 34 SD_CMD O
35 SD_CLK O 36 SD_DATA0 I/O
37 GND 38 RESERVED
39 RESERVED 40 TXD_AUX O
41 RXD_AUX I 42 DBG_TXD O
43 DBG_RXD I 44 RESERVED
45 DCD O 46 RI O
47 DTR I 48 CTS O
49 RTS I 50 RXD I
51 TXD O 52 SIM_GND
53 SIM_RST O 54 SIM_CLK O
55 SIM_DATA I/O 56 SIM_VDD O
57 SIM_PRESENCE I 58 RESERVED
59 VRTC I/O 60 VDD_EXT O
61 GND 62 GND
63 RF_ANT I/O 64 GND
65 GND 66 GND
67 VBAT I 68 VBAT I
69 VBAT I 70 VBAT I
71 RESERVED 72 RESERVED
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