Wi-Fi&BT Module Series
FG50V Hardware Design
FG50V_Hardware_Design 30 / 54
3.8. WLAN_SLP_CLK Interface
The 32.768 kHz clock is used in low power modes, such as IEEE power saving mode and sleep mode. It
serves as a timer to determine when to wake up the FG50V module to receive signals in various power
saving schemes, and to maintain basic logic operations when the module is in sleep mode.
Table 10: Pin Definition of WLAN_SLP_CLK Interface
Pin Name
Pin No.
I/O Description
Comment
WLAN_SLP_CLK
15
DI
WLAN sleep clock
If unused, keep this pin open.
3.9. Others Interfaces
3.9.1. SW_CTRL*
The following table shows the pin definition of SW_CTRL.
Table 11: Pin Definition of SW_CTRL
Pin Name
Pin No.
I/O
Description
Comment
SW_CTRL
57
DO
Switch control
1.8 V power domain.
Active high.
If unused, keep this pin open.
The following figure shows the reference design for SW_CTRL connection between FG50V and the host.
Figure 9: SW_CTRL Connection
