LTE-A Module Series
EM120R-GL&EM160R-GL Hardware Design
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3.8. PCIe Interface
EM120R-GL and EM160R-GL provide one integrated PCIe (Peripheral Component Interconnect Express)
interface which complies with the
PCI Express Specification, Revision 2.1
and supports 5 Gbps per lane.
The PCIe interface is used for data transmission, GNSS NMEA sentences output, software debugging
and firmware upgrade.
The following table shows the pin definition of PCIe interface.
Table 12: Pin Definition of PCIe Interface
“*” means under development.
Pin No. Pin Name
I/O
Description
Comment
55
PCIE_REFCLK_P
AI/AO
PCIe reference clock (+)
Require differential impedance
of 95
Ω.
53
PCIE_REFCLK_M AI/AO
PCIe reference clock (-)
49
PCIE_RX_P
AI
PCIe receive data (+)
Require differential impedance
of 95
Ω
47
PCIE_RX_M
AI
PCIe receive data (-)
43
PCIE_TX_P
AO
PCIe transmit data (+)
Require differential impedance
of 95
Ω
41
PCIE_TX_M
AO
PCIe transmit data (-)
50
PCIE_RST_N
DI
PCIe reset input.
Active low.
3.3 V power domain
52
PCIE_CLKREQ_N DO
PCIe clock request.
Active low.
3.3 V power domain
54
PCIE_WAKE_N
DO
PCIe wake up the host.
Active low.
3.3 V power domain
NOTE
