LTE Module Series
EG25-G Hardware Design
EG25-G_Hardware_Design 54 / 100
As SDIO signals are very high-speed, in order to ensure the SDIO interface design corresponds with the
SDIO 3.0 specification, please comply with the following principles:
It is important to route the SDIO signal traces with total grounding. The impedance of SDIO signal
trace is 50Ω (±10%).
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DCDC signals, etc.
It is recommended to keep matching length between CLK and DATA/CMD less than 1mm and total
routing length less than 50mm.
Keep termination resistors within 15Ω~24Ω on clock lines near the module and keep the route
distance from the module clock pins to termination resistors less than 5mm.
Make sure the adjacent trace spacing is 2 times of the trace width and bus capacitance is less than
15pF.
3.14.2.
BT Interface*
EG25-G supports a dedicated UART interface and a PCM interface for BT application.
Further information about BT interface will be added in future version of this document.
“*” means under development.
3.15.
SGMII Interface
EG25-G includes an integrated Ethernet MAC with an SGMII interface and two management interfaces,
and key features of the SGMII interface are shown below:
IEEE802.3 compliance
Support 10M/100M/1000M Ethernet work mode
Max data rate 150Mbps (DL) and 50Mbps (UL) in 4G LTE network.
Support VLAN tagging
Support IEEE1588 and Precision Time Protocol (PTP)
Can be used to connect to external Ethernet PHY like AR8033, or to an external switch
Management interfaces support dual voltage 1.8V/2.85V
NOTE
