LTE Standard Module Series
EC21 Mini PCIe Hardware Design
EC21_Mini_PCIe_Hardware_Design 29 / 67
AT+IPR
command can be used to set the baud rate of the main UART, and
AT+IFC
command can be
used to set the hardware flow control (hardware flow control is disabled by default). Please refer to
document [2]
for details.
3.7. PCM and I2C Interfaces
EC21 Mini PCIe provides one Pulse Code Modulation (PCM) digital interface and one I2C interface.
The following table shows the pin definition of PCM and I2C interfaces that can be applied in audio codec
design.
Table 10: Pin Definition of PCM and I2C Interfaces
EC21 Mini PCIe provides one PCM digital interface, which supports 16-bit linear data format and the
following modes:
Primary mode (short frame synchronization, works as either master or slave)
Auxiliary mode (long frame synchronization, works as master only)
In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports
256kHz, 512kHz, 1024kHz or 2048kHz PCM_CLK at 8kHz PCM_SYNC, and also supports 4096kHz
PCM_CLK at 16kHz PCM_SYNC. The following figure shows the timing relationship in primary mode with
8kHz PCM_SYNC and 2048kHz PCM_CLK.
Pin Name
Pin No.
I/O
Power Domain
Description
PCM_CLK
1)
45
IO
1.8V
PCM clock signal
PCM_DOUT
1)
47
DO
1.8V
PCM data output
PCM_DIN
1)
49
DI
1.8V
PCM data input
PCM_SYNC
1)
51
IO
1.8V
PCM frame synchronization
I2C_SCL
30
DO
1.8V
I2C serial clock.
Require external pull-up to 1.8V.
I2C_SDA
32
IO
1.8V
I2C serial data.
Require external pull-up to 1.8V.
NOTE
