LTE Standard Module Series
EC21 Mini PCIe Hardware Design
EC21_Mini_PCIe_Hardware_Design 30 / 67
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
MSB
125us
1
2
256
255
PCM_DIN
MSB
LSB
MSB
Figure 8: Timing in Primary Mode
In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC rising edge represents the MSB. In this mode, the PCM interface operates with a
256kHz, 512kHz, 1024kHz or 2048kHz PCM_CLK and an 8kHz, 50% duty cycle PCM_SYNC. The
following figure shows the timing relationship in auxiliary mode with 8kHz PCM_SYNC and 256kHz
PCM_CLK.
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
PCM_DIN
125us
MSB
1
2
16
15
LSB
Figure 9: Timing in Auxiliary Mode
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. In addition, EC21
Mini PCIe’s firmware has integrated the configuration on some PCM codec’s application with I2C interface.
Please refer to
document [2]
for details about
AT+QDAI
command.