LTE Standard Module Series
EC200U_Series_Hardware_Design 52 / 94
Table 25: Pin Definition of WLAN Interface
The SDIO interface rate is very high. To ensure that the interface design complies with the SDIO 1.1
specification, the following principles are recommended:
⚫
It is important to route the SDIO signal surrounded with ground on the layer and ground planes above
and below. The impedance of SDIO data trace is 50
Ω ±10 %.
⚫
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DC-DC signals, etc.
⚫
It is recommended to keep the trace length difference between WLAN_SDIO_CLK and
WLAN_SDIO_DATA [0:3]/ WLAN_SDIO_CMD less than 1 mm and the total routing length less than
50 mm.
⚫
Make sure the adjacent trace spacing is more than two times of the trace width and the load
capacitance of SDIO bus should be less than 15 pF.
Pin Name
Pin No.
I/O
Description
Comment
WLAN_SLP_CLK
118
DO
WLAN sleep clock
If unused, keep it open.
WLAN_PWR_EN
127
DO
WLAN power supply enable
control
1.8 V power domain.
If unused, keep them open.
SDIO2_DATA3
129
DIO
WLAN SDIO data bit 3
SDIO2_DATA2
130
DIO
WLAN SDIO data bit 2
SDIO2_DATA1
131
DIO
WLAN SDIO data bit 1
SDIO2_DATA0
132
DIO
WLAN SDIO data bit 0
SDIO2_CLK
133
DO
WLAN SDIO CLK
SDIO2_CMD
134
DO
WLAN SDIO command
WLAN_WAKE
135
DI
Wake up the module by an
external Wi-Fi module
1.8 V power domain.
If unused, keep them open.
WLAN_EN
136
DO
WLAN
function
enable
control
WLAN application interface conflicts with other functions, and please consult Quectel Technical
Supports for details.
NOTE
