LTE Module Series
BG96 Hardware Design
BG96_Hardware_Design 39 / 78
MCU/ARM
TXD
RXD
VDD_EXT
10K
VCC_MCU
4.7K
10K
VDD_EXT
TXD
RXD
RTS
CTS
DTR
RI
RTS
CTS
GND
GPIO
DCD
Module
GPIO
EINT
VDD_EXT
4.7K
GND
1nF
1nF
Figure 16: Reference Circuit with Transistor Circuit
Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.
3.11. PCM* and I2C* Interfaces
BG96 provides one Pulse Code Modulation (PCM*) digital interface and one I2C* interface. The following
table shows the pin definition of the two interfaces which can be applied on audio codec design.
Table 15: Pin Definition of PCM* and I2C* Interfaces
Pin Name
Pin No.
I/O
Description
Comment
PCM_CLK*
4
DO
PCM clock output
1.8V power domain
PCM_SYNC*
5
DO
PCM frame synchronization
output
1.8V power domain
PCM_IN*
6
DI
PCM data input
1.8V power domain
PCM_OUT*
7
DO
PCM data output
1.8V power domain
I2C_SCL*
40
OD
I2C serial clock
Require external pull-up to 1.8V
I2C_SDA*
41
OD
I2C serial data
Require external pull-up to 1.8V
NOTE
