Quectel BG772A-GL Hardware Design Download

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LPWA Module Series

BG772A-GL Hardware Design

BG772A-GL_Hardware_Design

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7.2. Recommended Footprint

Figure 33: Recommended Footprint (Top View)

1. For easy maintenance of the module, keep a distance of about 3 mm between the module and other

components on the motherboard.

2. All reserved pins must be kept open.
3. For stencil design requirements of the module, see

document [6]

NOTES

Summary of Contents for BG772A-GL

Page 1: ...BG772A GL Hardware Design LPWA Module Series Version 1 0 0 Date 2021 01 28 Status Preliminary www quectel com...

Page 2: ...r notice Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors it is possible that these functions and features could contain error...

Page 3: ...Quectel Transmitting reproducing disseminating and editing this document as well as using the content without permission are forbidden Offenders will be held liable for payment of damages All rights a...

Page 4: ...may cause interference on sensitive medical equipment so please be aware of the restrictions on the use of wireless devices when in hospitals clinics or other healthcare facilities Cellular terminals...

Page 5: ...GL Hardware Design BG772A GL_Hardware_Design 4 75 About the Document Revision History Version Date Author Description 2021 01 28 Besson RONG Ben JIANG Creation of the document 1 0 0 2021 01 28 Besson...

Page 6: ...rplane Mode 28 3 4 2 Power Saving Mode PSM 28 3 4 3 Extended Idle Mode DRX e I DRX 29 3 4 4 Sleep Mode 29 3 4 4 1 UART Application 29 3 5 Power Supply 30 3 5 1 Power Supply Pins 30 3 5 2 Decrease Volt...

Page 7: ...na Interface 54 5 3 Antenna Installation 55 5 3 1 Reference Design of RF Layout 55 5 3 2 Antenna Requirements 57 5 3 3 Recommended RF Connector for Antenna Installation 58 6 Electrical Reliability and...

Page 8: ...on of STATUS 46 Table 20 Default Behaviors of MAIN_RI 46 Table 21 Pin Definition of ADC Interfaces 47 Table 22 Characteristics of ADC Interfaces 47 Table 23 Pin Definition of GPIO Interfaces 48 Table...

Page 9: ...G772A GL Hardware Design BG772A GL_Hardware_Design 8 75 Table 42 Recommended Thermal Profile Parameters 74 Table 43 BG772A GL Packaging Specifications 75 Table 44 Related Documents 76 Table 45 Terms a...

Page 10: ...ference Design Translator Chip 43 Figure 18 Main UART Reference Design Transistor Circuit 43 Figure 19 Reference Circuit of PCM Application with Audio Codec 44 Figure 20 Reference Design of NET_STATUS...

Page 11: ...ation distance of 20cm to the human body FCC Certification Requirements According to the definition of mobile and fixed device is described in Part 2 1091 b this device is a mobile device And the foll...

Page 12: ...spect to 2 1093 and different antenna configurations For this device OEM integrators must be provided with labeling instructions of finished products Please refer to KDB784748 D01 v07 section 8 Page 6...

Page 13: ...provide information to the end user regarding how to install or remove this RF module in the user s manual of the end product which integrates this module The end user manual shall include all requir...

Page 14: ...pour le module pr c d du mot Contient ou d un libell semblable exprimant la m me signification comme suit Contient IC 10224A 2022BG772A ou o 10224A 2022BG772A est le num ro de certification du module...

Page 15: ...concurrent operation of WWAN and GNSS The solution adopted in the module is a form of coarse time division multiplexing TDM between WWAN and GNSS Rx chains Given the relaxed latency requirements of mo...

Page 16: ...ransmitting Power Class 3 23 dBm 2 7 dB for LTE FDD bands LTE Features Supports 3GPP Rel 14 Supports LTE Cat M1 and LTE Cat NB2 Supports 1 4 MHz RF bandwidth for LTE Cat M1 Supports 200 kHz RF bandwid...

Page 17: ...bugging and log output 115200 bps baud rate by default The default frame format is 8N1 8 data bits no parity 1 stop bit Support RTS and CTS hardware flow control AUX UART Used for RF calibration debug...

Page 18: ...n 17 75 2 3 Functional Diagram The following figure shows a block diagram of BG772A GL and illustrates the major functional parts Power management Baseband Radio frequency Peripheral interfaces Figure...

Page 19: ...2 4 Evaluation Board To facilitate application development with BG772A GL conveniently Quectel supplies the evaluation board EVB USB to RS 232 converter cables USB data cables earphone antennas and ot...

Page 20: ...th 94 LGA pads that can be connected to customers cellular application platforms The subsequent chapters will provide detailed description of interfaces listed below Power supply PON_TRIG interface U...

Page 21: ...LPWA Module Series BG772A GL Hardware Design BG772A GL_Hardware_Design 20 75 3 1 Pin Assignment The following figure shows the pin assignment of BG772A GL Figure 2 Pin Assignment Top View...

Page 22: ...pins should be connected to ground in the design 5 PCM and I2C interfaces are for VoLTE only 3 2 Pin Description The following tables show the pin definition of BG772A GL Table 4 Definition of I O Pa...

Page 23: ...25 27 28 30 31 43 47 52 56 58 66 73 75 84 86 88 89 Turn on off Pin Name Pin No I O Description DC Characteristics Comment PWRKEY 46 DI PU Turn on off the module VILmax 0 3 V VIHmin 1 0 V Reset Pin Na...

Page 24: ...n USIM_VDD 16 PO U SIM card power supply Vmax 1 9 V Vmin 1 7 V Only 1 8 V U SIM card is supported USIM_RST 15 DO PD U SIM card reset 1 8 V USIM_DATA 14 DIO PU U SIM card data 1 8 V USIM_CLK 13 DO PD U...

Page 25: ...liary UART transmit 1 8 V If this pin is unused keep it open AUX_RXD 82 DI PU Auxiliary UART receive 1 8 V AUX_CTS 70 DO PU Auxiliary UART clear to send 1 8 V AUX_RTS 59 DI PU Auxiliary UART request t...

Page 26: ...ral purpose input output 1 8 V If this pin is unused keep it open GPIO2 8 DIO PD General purpose input output 1 8 V GPIO3 9 DIO PD General purpose input output 1 8 V GPIO4 33 DIO PD General purpose in...

Page 27: ...E 41 DI PU Airplane mode control 1 8 V Pulled up by default When it is at low voltage level the module can enter airplane mode If this pin is unused keep it open AP_READY 77 DI PU Application processo...

Page 28: ...ng data and or network originated procedures within a certain delay dependent on the DRX cycle value Airplane Mode AT CFUN 4 or W_DISABLE pin can set the module into airplane mode where the RF functio...

Page 29: ...mand will not affect GNSS function 3 4 2 Power Saving Mode PSM BG772A GL module minimizes its power consumption through entering PSM The mode is similar to power off but the module remains registered...

Page 30: ...based on operator policies and if available the e I DRX cycle length value in the subscription data from the HSS may also provide different values of the e I DRX parameters than what was requested by...

Page 31: ...the host can be configured to high voltage level or low voltage level detection See AT QCFG apready in document 3 for details 3 5 Power Supply 3 5 1 Power Supply Pins BG772A GL provides VBAT_BB and VB...

Page 32: ...amic chip capacitor MLCC array should also be reserved due to its low ESR It is recommended to use three ceramic capacitors 100 nF 33 pF 10 pF for composing the MLCC array and place these capacitors c...

Page 33: ...n collector driver to control the PWRKEY A simple reference circuit is illustrated in the following figure Figure 5 Turn on the Module by Using Driving Circuit Another way to control the PWRKEY is by...

Page 34: ...Module Series BG772A GL Hardware Design BG772A GL_Hardware_Design 33 75 Figure 6 Turn on the Module by Using Keystroke The power up scenario is illustrated in the following figure Figure 7 Power up Ti...

Page 35: ...through PWRKEY Turn off the module through AT QPOWD 3 6 3 1 Turn off Module through PWRKEY Drive the PWRKEY pin low for 650 1500 ms and then releasing it the module will execute power down procedure...

Page 36: ...Pin Definition of RESET_N The reset timing is illustrated in the following figure Figure 9 Reset Timing The recommended circuit is similar to the PWRKEY control circuit An open drain collector driver...

Page 37: ...G BG772A GL provides one PON_TRIG pin which is used to wake up the module from PSM When the pin detects high level for minimum assertion time 100 s the module will wake up from PSM Table 10 Pin Defini...

Page 38: ...face circuitry meets ETSI and IMT 2000 requirements Table 11 Pin Definition of U SIM Interface Pin Name Pin No I O Description Comment USIM_DET 44 DI PD U SIM card hot plug detect 1 8 V power domain U...

Page 39: ...interface with an 8 pin U SIM card connector Figure 13 Reference Circuit of U SIM Interface with an 8 Pin U SIM Card Connector If U SIM card detection function is not needed keep USIM_DET unconnected...

Page 40: ...o reserve series resistors for the U SIM signals of the module The 33 pF capacitors are used for filtering interference of EGSM900 Note that the U SIM peripheral circuit should be close to the U SIM c...

Page 41: ...ace must be as short as possible To meet USB 2 0 specification comply with the following principles while designing the USB interface It is important to route the USB signal traces as differential pai...

Page 42: ...e format is 8N1 8 data bits no parity 1 stop bit The debug UART interface supports 9600 bps 19200 bps 38400 bps 57600 bps 115200 bps 230400 bps 460800 bps 921600 bps and 3000000 bps baud rates and the...

Page 43: ...translator should be used if customers application is equipped with a 3 3 V UART interface The following figure shows a reference design of the main UART interface MAIN_RI 76 DO PU Main UART ring ind...

Page 44: ...uit is shown as below For the design of circuits in dotted lines refer to that of circuits in solid lines but pay attention to the direction of connection Figure 18 Main UART Reference Design Transist...

Page 45: ...es The following figure shows a reference design of PCM and I2C interfaces with an external codec IC Figure 19 Reference Circuit of PCM Application with Audio Codec PCM and I2C interfaces support VoLT...

Page 46: ...status Table 17 Pin Definition of NET_STATUS Table 18 Working State of NET_STATUS A reference circuit is shown in the following figure Figure 20 Reference Design of NET_STATUS Pin Name Pin No I O Desc...

Page 47: ...it of STATUS Figure 21 Reference Design of STATUS 3 15 Behaviors of MAIN_RI AT QCFG risignaltype physical can be used to configure MAIN_RI behavior No matter on which port URC is presented URC will tr...

Page 48: ...d the voltage value on ADC0 pin AT QADC 1 be used to read the voltage value on ADC1 pin For more details about the AT command see document 4 To improve the accuracy of ADC voltage values the trace of...

Page 49: ...erfaces The module provides seven general purpose input and output GPIO interfaces AT QCFG gpio can be used to configure the status of GPIO pins For more details about the AT command see document 3 Ta...

Page 50: ...l of external antenna tuners Table 24 Pin Definition of GRFC Interfaces Table 25 Truth Table of GRFC Interfaces Pin Name Pin No Description Comments GRFC1 83 Generic RF controller 1 8 V power domain G...

Page 51: ...ne is switched off It has to be switched on via AT command The module does not support concurrent operation of WWAN and GNSS For more details about GNSS engine technology and configurations see docume...

Page 52: ...tes after executing cold start command 4 3 Layout Guidelines The following layout guidelines should be taken into account in application designs Maximize the distance between GNSS antenna and main ant...

Page 53: ...terface is shown below Table 27 Pin Definition of Main Antenna Interface 5 1 2 Operating Frequency Table 28 BG772A GL Operating Frequency Pin Name Pin No I O Description Comment ANT_MAIN 26 AIO Main a...

Page 54: ...er RF performance and the type matching components R1 C1 C2 should be placed as close to the antenna as possible The capacitors are not mounted by default Figure 22 Reference Design of Main Antenna In...

Page 55: ...Pin Definition of GNSS Antenna Interface 5 2 2 GNSS Operating Frequency Table 30 GNSS Operating Frequency 5 2 3 Reference Design of GNSS Antenna Interface A reference design of GNSS antenna interface...

Page 56: ...f RF traces is usually determined by the trace width W the materials dielectric constant height from the reference ground to the signal layer H and the clearance between RF traces and grounds S Micros...

Page 57: ...ed as thermal relief pads and should be fully connected to ground The distance between the RF pins and the RF connector should be as short as possible and all the right angle traces should be changed...

Page 58: ...supported as the use of active antenna may generate harmonics which will affect the GNSS performance Antenna Type Requirements GNSS 1 Frequency range 1559 1609 MHz Polarization RHCP or linear VSWR 2 T...

Page 59: ...Installation If RF connector is used for antenna connection it is recommended to use U FL R SMT connectors provided by HIROSE Figure 28 Dimensions of the U FL R SMT Connector Unit mm U FL LP serial co...

Page 60: ...BG772A GL Hardware Design BG772A GL_Hardware_Design 59 75 The following figure describes the space factor of mated connector Figure 30 Space Factor of Mated Connector Unit mm For more details visit h...

Page 61: ...Absolute Maximum Ratings 6 2 Power Supply Ratings Table 33 Power Supply Ratings Parameter Min Max Unit VBAT_BB 0 2 4 5 V VBAT_RF 4 6 V USB_VBUS 1 19 2 0 V Voltage at Digital Pins 0 3 2 0 V Parameter D...

Page 62: ...temperature range the module remains the ability to establish and maintain functions such as voice SMS and data transmission without any unrecoverable malfunction Radio spectrum and radio network are...

Page 63: ...ep Mode USB UART disconnected LTE Cat M1 DRX 1 28 s TBD mA LTE Cat NB1 DRX 1 28 s TBD mA LTE Cat M1 e I DRX 81 92 s PTW 2 56 s DRX 1 28 s TBD mA LTE Cat NB1 e I DRX 81 92 s PTW 2 56 s DRX 1 28 s TBD m...

Page 64: ...A LTE FDD B28A dBm TBD TBD mA LTE FDD B28B dBm TBD TBD mA LTE FDD B66 dBm TBD TBD mA LTE Cat NB2 data transfer GNSS OFF LTE FDD B1 dBm TBD TBD mA LTE FDD B2 dBm TBD TBD mA LTE FDD B3 dBm TBD TBD mA LT...

Page 65: ...alf sky Real network Passive antenna TBD mA Half sky Real network Active antenna TBD mA 6 5 Digital I O Characteristic Table 37 1 8 V I O Requirements Table 38 U SIM 1 8 V I O Requirements LTE FDD B66...

Page 66: ...RF receiving sensitivity of BG772A GL Table 40 BG772A GL Conducted RF Receiving Sensitivity VOL Output low voltage 0 0 38 V Frequency Bands Max RF Output Power Min RF Output Power LTE FDD B1 B2 B3 B4...

Page 67: ...by Cat M1 only LTE FDD B8 TBD 99 8 TBD 107 5 LTE FDD B12 TBD 99 3 TBD 107 5 LTE FDD B13 TBD 99 3 TBD 107 5 LTE FDD B17 2 Not Supported TBD 107 5 LTE FDD B18 TBD 102 3 TBD 107 5 LTE FDD B19 TBD 102 3 T...

Page 68: ...sitive components Proper ESD handling and packaging procedures must be applied throughout the processing handling and operation of any application that incorporates the module The following table show...

Page 69: ...7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module All dimensions are measured in millimeter mm and the dimensional tolerances are 0 05 mm unless otherwise specifie...

Page 70: ...A Module Series BG772A GL Hardware Design BG772A GL_Hardware_Design 69 75 Figure 32 Bottom Dimensions Bottom View The package warpage level of the module conforms to the JEITA ED 7306 standard Pin 1 N...

Page 71: ...nded Footprint Figure 33 Recommended Footprint Top View 1 For easy maintenance of the module keep a distance of about 3 mm between the module and other components on the motherboard 2 All reserved pin...

Page 72: ...ardware_Design 71 75 7 3 Top and Bottom Views Figure 34 Top and Bottom View of the Module Images above are for illustration purpose only and may differ from the actual module For authentic appearance...

Page 73: ...module must be processed in reflow soldering or other high temperature operations within 168 hours Otherwise the module should be stored in an environment where the relative humidity is less than 10...

Page 74: ...DEC J STD 033 for baking procedure 8 2 Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil thus making the paste fill the stencil openings and then penetr...

Page 75: ...e 8 3 Packaging BG772A GL is packaged in a vacuum sealed bag which is ESD protected The bag should not be opened until the devices are ready to be soldered onto the application The following figures s...

Page 76: ...re_Design 75 75 Figure 36 Tape Dimensions Figure 37 Reel Dimensions Table 43 BG772A GL Packaging Specifications MOQ for MP Minimum Package 500 Minimum Package x 4 2000 500 Pieces Size 370 mm 350 mm 56...

Page 77: ...Commands Manual for BG772A GL Module 4 Quectel_BG772A GL_AT_Commands_Manual AT Commands Manual of BG772A GL Module 5 Quectel_RF_Layout_Application_Note RF Layout Application Note 6 Quectel_Module_Sec...

Page 78: ...Low Noise Amplifier LPF Low Pass Filter LTE Long Term Evolution MO Mobile Originated MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol Data Unit PPP Poi...

Page 79: ...x Maximum Voltage Value Vnom Nominal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level...

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