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BAUD RATE SELECTION

V I . A D D R E S S I N G

          T h e     Q S - 2 0 0 M / Q S - 3 0 0 M   u s e s   8   I / O   a d d r e s s   l o c a t i o n s
p e r   c h a n n e l .     F u l l   s i x t e e n   b i t   a d d r e s s   d e c o d i n g   a l l o w s
b a s e   a d d r e s s   s e l e c t i o n s   i n   t h e   r a n g e   0 0 0 0   -   F F F F   H e x .
Two six position switches, SW1 & SW2 are used to specify
t h e   b a s e   a d d r e s s   o f   t h e   a d a p t e r .     S W 1   c o n t r o l s   t h e
a d d r e s s   s e t t i n g   f o r   A 1 5 - A 1 0   t h r o u g h   p o s i t i o n s   1 - 6
r e s p e c t i v e l y .     S w i t c h   S W 2 ,   p o s i t i o n s   1 - 5   c o n t r o l   a d d r e s s
s e l e c t i o n s   f o r   A 9 - A 5 .   T h e   r e m a i n i n g   a d d r e s s   i n p u t s   a r e
used by the adapter to determine the channel and register
being accessed.

A switch in the "ON" position indicates that the
c o r r e s p o n d i n g a d d r e s s b i t b e a l o g i c 0 f o r s e l e c t i o n .
A s w i t c h i n t h e " O F F " p o s i t i o n f o r c e s t h e c o r r e s p o n d i n g
address bit to be a logic 1 for selection. Some
example switch settings for the QS-200M/QS-300M are shown
in figures 16 and 17.

The base address of each channel is incremented by a
f a c t o r o f 8 f r o m t h e b a s e a d d r e s s o f t h e a d a p t e r .
T h e r e f o r e 3 2 a d d r e s s l o c a t i o n s a r e u s e d b y t h e Q S - 2 0 0 M /
QS-300M.

PORT

ADDRESS RANGE

1 Base 0 - Base 7
2 Base 8 - Base 15
3 Base 16 - Base 23
4 Base 24 - Base 31

+--------------------+ +--------------------+
| 1 2 3 4 5 6 | | 1 2 3 4 5 6 |
On| +-++-++-++-++-++-+ | On| +-++-++-++-++-++-+ |
| |_||_||_||_||_||_| | | | || ||_||_||_|| | |
| | || || || || || | | | |_||_|| || || || | |
Off| +-++-++-++-++-++-+ | Off| +-++-++-++-++-++-+ |
+--------------------+ +--------------------+
SW1 SW2

Figure 16. Factory address switch settings.
Address shown is 0300H.

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Summary of Contents for QS-200M

Page 1: ...hough every attempt has been made to guarantee the accuracy of this manual Qua Tech Inc assumes no l i a b i l i t y f o r d a m a g e s r e s u l t i n g f r o m e r r o r s i n t h i s document Qua Tech Inc reserves the right to edit or append to this document at any time without notice Please complete the following information and retain for your records Have this information available when req...

Page 2: ...R 5 C FIFO CONTROL REGISTER 7 D LINE CONTROL REGISTER 8 E MODEM CONTROL REGISTER 10 F LINE STATUS REGISTER 11 G MODEM STATUS REGISTER 13 H SCRATCHPAD REGISTER 14 IV FIFO INTERRUPT MODE OPERATION 14 V BAUD RATE SELECTION 14 VI ADDRESSING 16 VII INTERRUPTS 18 INTERRUPT STATUS REGISTER 19 VIII OUTPUT CONFIGURATIONS 20 IX EXTERNAL CONNECTIONS 21 X INSTALLATION 22 XI SPECIFICATIONS 22 For optional 1655...

Page 3: ...Parity options 9 Figure 10 Word length and stop bit options 9 Figure 11 MODEM control register 10 Figure 12 Line status register 11 Figure 13 MODEM status register 13 Figure 14 Clock options 15 Figure 15 Divisor latch options 15 Figure 16 Address selection switches 16 Figure 17 Address selection examples 17 Figure 18 Interrupt selection jumper 18 Figure 19 Interrupt status register selection 19 Fi...

Page 4: ... range o f a d d r e s s c h o i c e s b e t w e e n 0 a n d F F F F h e x T h e Q S 2 0 0 M Q S 3 0 0 M h a s t h e o p t i o n o f s e l e c t i n g o n e o f s i x possible Interrupt Request lines IRQ 2 IRQ 7 A hardware selectable clock divider is also available for producing unusual baud rates II BOARD DESCRIPTION A component diagram of the QS 200M QS 300M is shown i n f i g u r e 1 T h e b a ...

Page 5: ...BOARD DESCRIPTION Figure 1 QS 200M QS 300M board layout ...

Page 6: ...y bits Independent and prioritized transmit receive and status interrupts Transmitter clock output to drive receive logic External receiver clock input The following pages provide a brief summary of the internal registers available within the 16450 and 16550 ACEs The registers are addressed as shown in figure 2 below Registers and functions specific to the 16550 will be marked with an asterisk DLA...

Page 7: ...errupt When set logic 1 enables interrupt on clear to send data set ready ring indicator and data carrier detect ELSI Receiver Line Status Interrupt When set logic 1 enables interrupt on overrun parity framing errors and break indication ETBEI Transmitter Holding Register Empty Interrupt When set logic 1 enables interrupt on transmitter register empty ERBFI Received Data Available Interrupt When s...

Page 8: ...le When logic 1 indicates FIFO mode enabled IIDx Interrupt Identification Indicates highest priority interrupt pending if a n y S e e I P a n d f i g u r e 5 N O T E I I D 2 i s always a logic 0 in character mode IP Interrupt Pending W h e n l o g i c 0 i n d i c a t e s t h a t a n i n t e r r u p t i s p e n d i n g a n d t h e c o n t e n t s o f t h e i n t e r r u p t identification register ...

Page 9: ... mode Indicates the receiver FIFO trigger level has been reached The interrupt is reset when the FIFO drops below the the trigger level Character Timeout FIFO mode only Indicates no characters have been removed from or input to the receiver FIFO for the last four character times and there is data present in the r e c e i v e r F I F O T h e i n t e r r u p t i s c l e a r e d b y reading the recei...

Page 10: ...rigger level for the receiver FIFO interrupt as given in figure 7 below RCVR FIFO RXT1 RXT0 Trigger level bytes 0 0 1 0 1 4 1 0 8 1 1 14 Figure 7 FIFO Trigger Levels DMAM DMA Mode Select When set logic 1 RxRDY and TxRDY change from mode 0 to mode 1 for DMA transfers DMA mode not supported on QS 200M QS 300M XRST Transmit FIFO Reset When set logic 1 all bytes in the transmitter FIFO are cleared and...

Page 11: ...e r a r e w r i t t e n t o o r t h e b i t s w i l l b e ignored I I I D LINE CONTROL REGISTER D7 DLAB Divisor latch access bit D6 BKCN Break control D5 STKP Stick parity D4 EPS Even parity select D3 PEN Parity enable D2 STB Number of stop bits D1 WLS1 Word length select D0 WLS0 Figure 8 Line Control Register bit definitions DLAB Divisor Latch Access Bit DLAB must be set to logic 1 to access the ...

Page 12: ... and figure 9 STKP EPS PEN Parity x x 0 None 0 0 1 Odd 0 1 1 Even 1 0 1 Logic 1 1 1 1 Logic 0 Figure 9 16450 Parity Selections STB Number of Stop Bits Sets the number of stop bits transmitted See WLSx and figure 10 WLSx Word Length Select Determines the number of bits per transmitted word See STB and figure 10 STB WLS1 WLS0 Word length Stop bits 0 0 0 5 bits 1 0 0 1 6 bits 1 0 1 0 7 bits 1 0 1 1 8...

Page 13: ...receive data paths Transmitter and receiver i n t e r r u p t s s t i l l o p e r a t e n o r m a l l y M O D E M c o n t r o l i n t e r r u p t s a r e a v a i l a b l e b u t a r e n o w controlled through the MODEM control register B i t s O U T 2 O U T 1 R T S a n d D T R p e r f o r m i d e n t i c a l functions on their respective outputs When these b i t s a r e s e t l o g i c 1 i n t h e...

Page 14: ...a m i n g e r r o r s o r b r e a k i n d i c a t i o n s i n t h e r e c e i v e r FIFO FFRX is reset by reading the line status register TEMT Transmitter Empty Indicates the transmitter holding register or FIFO and the transmitter shift register are empty and are ready to receive new data TEMT i s r e s e t b y w r i t i n g a c h a r a c t e r t o t h e transmitter holding register THRE Transmi...

Page 15: ...es to the mark state logic 1 and a valid start bit is received FE Framing Error Indicates the received character had an invalid stop bit The stop bit following the last data or parity bit was a 0 bit spacing level PE Parity Error Indicates that the received data does not have the correct parity OE Overrun Error Indicates the receive buffer was not read before t h e n e x t c h a r a c t e r w a s ...

Page 16: ...input DSR Data Set Ready Complement of the DSR input CTS Clear To Send Complement of the CTS input Bits DDCD TERI DDSR and DCTS are the sources of MODEM status interrupts These bits are reset when the MODEM status register is read DDCD Delta Data Carrier Detect I n d i c a t e s t h e D a t a C a r r i e r D e t e c t i n p u t h a s changed state TERI Trailing Edge Ring Indicator Indicates the Ri...

Page 17: ...is cleared when the FIFO is empty V BAUD RATE SELECTION The 16450 ACE determines the baud rate of the serial o u t p u t a n d u s e s a c o m b i n a t i o n o f t h e c l o c k i n p u t frequency and the value written to the divisor latches Standard PC PC XT PC AT and PS 2 serial interfaces use an input clock of 1 8432 MHz To increase versatility the QS 200M QS 300M uses an 18 432 MHz crystal a...

Page 18: ...be set at 10 18 432 MHz 10 1 8432 MHz Desired Divisor Error Between Desired Baud Rate Latch Value and Actual Value 50 2304 75 1536 110 1047 0 026 150 768 300 384 600 192 1200 96 1800 64 2000 58 0 69 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 2 86 Figure 15 Divisor latch settings for common baud r a t e s u s i n g a n 1 8 4 3 2 M H z i n p u t c l o c k For compatibility conne...

Page 19: ...eing accessed A switch in the ON position indicates that the corresponding address bit be a logic 0 for selection A switch in the OFF position forces the corresponding address bit to be a logic 1 for selection Some example switch settings for the QS 200M QS 300M are shown in figures 16 and 17 The base address of each channel is incremented by a f a c t o r o f 8 f r o m t h e b a s e a d d r e s s...

Page 20: ... 0 0 0 2 1 0 0 0 0 3 0 0 0300H BASE ADDRESS 06A0H 1 2 3 4 5 6 1 2 3 4 5 6 On _ _ _ _ _ _ _ _ _ _ _ Off 0 0 0 0 0 4 2 0 8 0 2 0 6 A 0 06A0H BASE ADDRESS 5220H 1 2 3 4 5 6 1 2 3 4 5 6 On _ _ _ _ _ _ _ _ _ _ _ Off 0 4 0 1 0 0 2 0 0 0 2 5 2 2 0 5220H Figure 17 Address switch selection examples ...

Page 21: ...changed through a hardware jumper J3 as shown below Source 1 7 _ _ IRQ 2 9 _ _ IRQ 3 _ _ IRQ 4 J3 _ _ IRQ 5 _ _ IRQ 6 _ _ IRQ 7 6 12 Figure 18 Interrupt level selection jumper T h e Q S 2 0 0 M Q S 3 0 0 M i s a l s o e q u i p p e d w i t h a n interrupt sharing circuit This circuit allows the QS 200M QS 300M to share its interrupt with other Qua Tech adapters supporting this feature ...

Page 22: ...egister a n d a l l o f t h e 1 6 4 5 0 1 6 5 5 0 s b e h a v e n o r m a l l y W h e n position 6 is in the ON position the Interrupt Status register overrides the ACEs internal Scratchpad register I n t h i s m o d e a n i n p u t f r o m t h e S c r a t c h p a d r e g i s t e r address BASE ADDRESS 7 of any channel will return the interrupt status of the entire card SW2 1 2 3 4 5 6 ON Interrup...

Page 23: ...is set logic 1 the transmitter d r i v e r i s e n a b l e d f o r o u t p u t o n t h e c h a n n e l W h e n cleared logic 0 the transmitter output enters a high impedance state Full duplex operation is restored by removing the associated jumper C A U T I O N W h e n o p e r a t i n g i n h a l f d u p l e x m o d e t h e transmitter must be disabled before receiving any information Failure to d...

Page 24: ...EXTERNAL CONNECTIONS IX EXTERNAL CONNECTIONS Figure 22 Output Connectors ...

Page 25: ...ace system cover XI SPECIFICATIONS Bus interface IBM 8 bit bus PC XT Dimensions 8 25 x 3 9 Controllers 4 16450 Asynchronous Communication Elements Transmit drivers MC3487 or compatible Receive buffers MC3486 or compatible RS 422 interface 4 RJ 11 shielded connectors I O Address range 0000 FFFFH See section VI Interrupt levels IRQ 2 9 3 7 Power requirements I T I MS Supply 501mA 576mA 5 Volts 12 Vo...

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