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FUNCTIONAL DESCRIPTION

M O D E M S T A T U S R E G I S T E R

DCD - Data Carrier Detect:

Complement of the DCD input.

RI - Ring Indicator:

Complement of the RI input.

DSR - Data Set Ready:

Complement of the DSR input.

CTS - Clear To Send:

Complement of the CTS input.

B i t s D D C D , T E R I , D D S R , a n d D C T S a r e t h e s o u r c e s o f
M O D E M s t a t u s i n t e r r u p t s . T h e s e b i t s a r e r e s e t w h e n
the MODEM status register is read.

DDCD - Delta Data Carrier Detect:

I n d i c a t e s t h e D a t a C a r r i e r D e t e c t ( D C D ) i n p u t
has changed state.

TERI - Trailing Edge Ring Indicator:

I n d i c a t e s t h e R i n g I n d i c a t o r ( R I ) i n p u t h a s
changed from a low to a high state.

DDSR - Delta Data Set Ready:

I n d i c a t e s t h e D a t a S e t R e a d y ( D S R ) i n p u t h a s
changed state.

DCTS - Delta Clear To Send:

I n d i c a t e s t h e C l e a r t o S e n d ( C T S ) i n p u t h a s
changed state.

Summary of Contents for DS-302

Page 1: ...nty rights Although every attempt has been made to guarantee the accuracy of this manual Quatech Inc assumes no liability for damages resulting from errors in this document Quatech Inc reserves the ri...

Page 2: ...DENTIFICATION REGISTER 5 FIFO CONTROL REGISTER 7 LINE CONTROL REGISTER 8 MODEM CONTROL REGISTER 10 LINE STATUS REGISTER 11 MODEM STATUS REGISTER 13 SCRATCHPAD REGISTER 14 FIFO INTERRUPT MODE OPERATION...

Page 3: ...elections 15 Figure 8 Divisor latch options 15 Figure 9 Address selection switches 16 Figure 10 Address selection examples 17 Figure 11 Channel enable disable selection 17 Figure 12 System interrupt c...

Page 4: ...t i n g a n d o r s h a r i n g o n e o f s i x p o s s i b l e interrupt request lines IRQ 2 3 4 5 6 7 II BOARD DESCRIPTION A component diagram of the DS 202 DS 302 showing the locations of the 16450...

Page 5: ...Figure 1 DS 202 DS 302 component layout...

Page 6: ...ioritized transmit receive and status interrupts The following pages provide a brief summary of the internal registers available within the 16450 and 16550 ACEs The registers are addressed as shown in...

Page 7: ...or and data carrier detect ELSI Receiver Line Status Interrupt When set logic 1 enables interrupts on o v e r r u n p a r i t y f r a m i n g e r r o r s a n d b r e a k indication ETBEI Transmitter H...

Page 8: ...cation Indicates highest priority interrupt pending if a n y S e e I P a n d f i g u r e 3 N O T E I I D 2 i s always a logic 0 in the 16450 and in the 16550 character mode IP Interrupt Pending W h e...

Page 9: ...mode Indicates the receiver FIFO trigger level has been reached The interrupt is reset when the FIFO drops below the the trigger level Character Timeout FIFO mode only Indicates no characters have bee...

Page 10: ...e l f o r t h e F I F O interrupt as given in figure 4 below RCVR FIFO RXT1 RXT0 Trigger level bytes 0 0 1 0 1 4 1 0 8 1 1 14 Figure 4 FIFO trigger levels DMAM DMA Mode Select When set logic 1 RxRDY a...

Page 11: ...O c o n t r o l r e g i s t e r a r e w r i t t e n t o o r t h e b i t s w i l l b e ignored LINE CONTROL REGISTER D7 DLAB Divisor latch access bit D6 BKCN Break control D5 STKP Stick parity D4 EPS E...

Page 12: ...TKP and figure 5 STKP EPS PEN Parity x x 0 None 0 0 1 Odd 0 1 1 Even 1 0 1 Logic 1 1 1 1 Logic 0 Figure 5 16450 16550 parity selections STB Number of Stop Bits Defines the number of stop bits per char...

Page 13: ...d t h r o u g h t h e M O D E M c o n t r o l register B i t s O U T 2 O U T 1 R T S a n d D T R p e r f o r m i d e n t i c a l functions on their respective outputs When these b i t s a r e s e t l...

Page 14: ...a k i n d i c a t i o n s i n t h e r e c e i v e r FIFO FFRX is reset by reading the line status register TEMT Transmitter Empty Indicates the transmitter holding register or F I F O a n d t h e t r...

Page 15: ...til SIN goes to the mark state logic 1 and a valid start bit is received FE Framing Error Indicates the received character had an invalid stop bit The stop bit following the last data or parity bit wa...

Page 16: ...To Send Complement of the CTS input Bits DDCD TERI DDSR and DCTS are the sources of MODEM status interrupts These bits are reset when the MODEM status register is read DDCD Delta Data Carrier Detect...

Page 17: ...ty IV BAUD RATE SELECTION The 16450 16550 ACE determines the baud rate of t h e s e r i a l o u t p u t u s i n g a c o m b i n a t i o n o f t h e i n p u t clock frequency and the value written to t...

Page 18: ...432 MHz 10 1 8432 MHz Desired Divisor Error Between Desired Baud Rate Latch Value and Actual Value 50 2304 75 1536 110 1047 0 026 150 768 300 384 600 192 1200 96 1800 64 2000 58 0 69 2400 48 3600 32 4...

Page 19: ...F F position requires the address bit to be 1 Address lines A10 A15 must be 0 for port selection Some address selection examples are given in figure 10 J u m p e r J 4 i s u s e d t o i n d e p e n d...

Page 20: ...8H 1 2 3 4 5 6 7 8 ON _ _ _ _ _ _ _ _ 0 2 1 8 4 2 0 8 BASE ADDRESS 3 E 8 03E8H 1 2 3 4 5 6 7 8 ON _ _ _ _ _ _ _ _ 0 2 0 8 4 2 0 0 BASE ADDRESS 2 E 0 02E0H Figure 10 Address selection examples J4 3 _ _...

Page 21: ...n n e l 1 J 6 f o r channel 2 An additional feature of the DS 202 DS 302 is the ability to share one interrupt level between both communication channels or to share an interrupt level with another Qu...

Page 22: ...ceiver RCLK ___ DTR RxD ___ RS 422 485 DSR Receiver ___ DCD __ RI 16450 Figure 14 Output control block diagram Auxiliary Channel Configuration The function of jumpers J8 and J10 is to control t h e s...

Page 23: ...16b Transmission of XCLK can be used to synchronize communications with a peripheral or to provide a shift clock to a receiver XCLK is transmitted by connecting pins 5 and 6 of the jumper block figure...

Page 24: ...XCLK transmission XCLK RCLK loopback RCLK reception AUXOUT RTS XCLK 4 _ _ _ 6 1 _ _ _ 3 CTS RCLK AUXIN c RTS CTS loopback XCLK RCLK loopback AUXOUT AUXIN loopback Figure 16 Auxiliary channel configur...

Page 25: ...h i m p e d a n c e state If the jumper is installed between pins 2 and 6 t h e l o g i c a l s e n s e o f D T R i s i n v e r t e d T h a t i s clearing DTR logic 0 enables the transmitter drivers w...

Page 26: ...RIPTION 1 AUXOUT When combine with AUXOUT provides the auxiliary channel output defined by jumper J8 J10 2 TxD When combined with TxD provides the serial data output 3 GND Chassis ground 4 RxD When co...

Page 27: ...5 Replace system cover X SPECIFICATIONS Bus interface ISA 8 bit bus Controllers 2 16450 Asynchronous Communication Elements 16550 optional Interface 2 D 9 female connectors Transmit drivers MC3487 or...

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