Quantum Q250 Technical Reference Manual Download

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Summary of Contents for Q250

Page 1: ...Q200 Series Intelligent Disk Drives Technical Reference Manual For Q250 Q280 Disk Drives...

Page 2: ...Q200 SERIEStm INTELLIGENT DISK DRIVES Q250jQ280 DISK DRIVES Technical Reference Manual Publication No 81 45528 REV A...

Page 3: ...same manner as spare parts Publication No 81 45528 Rev KL587 UL CSA VDE UL recognition granted under File No E78016 CSA certification granted under File Nos LR496896 8 and LR496896 11 VDE certificatio...

Page 4: ...e 2 8 2 2 4 SCSI Bus Signal Descriptions 2 10 2 2 S SCSI Bus Timing 2 11 2 2 6 Power Requirements 2 14 2 2 7 Shorting Plug Options 2 16 2 2 8 Flex Circuit 2 19 2 3 PCB Functional Elements 2 19 2 3 1 P...

Page 5: ...the Drive Using the Defect Lists 4 9 4 3 Grounding Electrostatic Discharges and EMI 4 10 SECTION 5 MAINTENANCE 5 1 5 1 Maintenance Precautions 5 1 5 2 Level 1 Maintenance 5 1 5 3 Level 2 Maintenance...

Page 6: ...it Waveforms 2 22 2 25 2 28 DICEY Block Diagram 2 31 Power Up Sequence 2 34 Read Command Sequence 2 35 write Command Sequence 2 36 Printed Circuit Board Parts Locations PCB 7 3 2 Schematic PCB 7 Sheet...

Page 7: ...2 1 2 2 2 3 4 1 5 1 LIS T o F TAB L E S J1 Pin Assignments DC Power Requirements Microprocessors and Buffer RAM Available Spare and Defective Sectors Test Connector J5 Signals vi 2 9 2 15 2 32 4 8 5 5...

Page 8: ...ives enable high data throughput o Seeks are initiated immediately other commands are processed simultaneously o 14 KByte FIFO data buffer balances the transfer of data to and from the SCSI bus as wel...

Page 9: ...n comparison with other drives which use a dedicated servo surface In addition conservative linear bit and track densities ensure high data integrity Logical block sizes of 512 1024 and 2048 bytes are...

Page 10: ...s a mounting surface for the rest of the drive mechanism PCB and shock mount brackets See Figure 2 1 for relative locations yo ST K ASSEMBLY r HEADS ACTUATOR UPPER AND LOWER MAGNETS FACEPLATE DISK CLA...

Page 11: ...embly balance each other so that the mass center of the entire stack is at the center of the mounting hub The heads are mini composite slider type heads mounted to Whitney style spring steel flexures...

Page 12: ...nt outside air from entering the drive through the bearing core or along the bearing shaft Motor components are processed and coated to eliminate dust chips and oxides and final assembly is in a Class...

Page 13: ...mble flushes the ECC buffers in DICEY within the servo wedges are the servo tracks three times as many as the data tracks written in staggered sequence so they don t overlap on the disk In a wedge a s...

Page 14: ...UT T STo A 105 c J 104 rr w I S Y N C 103 PRE AMB LE I e TRACK NO 102 101 S Y N C P 0 S T DATA 512 BYTES 452us DETAIL OF A BURST E C C CHECKSUM HEAD NO BURSTS A C SECTOR NO BURSTS B D P 0 S T LOGICAL...

Page 15: ...ecalibrated the actuator seeks to the inner outer and middle tracks at each location servo burst amplitude measurements are made and from these the microprocessor calculates and stores adaptive gain p...

Page 16: ...SCSI data is accumulated in buffer RAM via DMA transfers As the disk is being read from data is also stored in RAM After a full sector is read the data is checked with the error correcting code at th...

Page 17: ...ransitions on the disk 2 2 3 SCSI Bus Physical Interface A 50 pin connector is provided at position J1 on the PCB for con necting to the standard SCSI bus See Figures 2 5 and 2 9 The standard SCSI sin...

Page 18: ...igure 2 5 Jl Connector Table 2 1 Jl Pin Assignments Signal Name 2 Data Bit 0 DBO 4 Data Bit 1 DBl 6 Data Bit 2 DB2 8 Data Bit 3 DB3 10 Data Bit 4 DB4 12 Data Bit 5 DB5 14 Data Bit 6 DB6 16 Data Bit 7...

Page 19: ...er devices on the bus unplug all three terminator packages If the additional terminators are not removed the bus drivers may be damaged because they will sink more current from the 5 V supply than the...

Page 20: ...control signals and nine signals that comprise an 8 bit DATA BUS with parity Each of the signals is described briefly below BSY BUSY An oR tied signal that indicates that the bus is being used SEL SE...

Page 21: ...ted in the event of 5 V failure 2 2 5 SCSI Bus Timing Delay time measurements for each SCSI device are calculated from signal conditions existing at that device s own SCSI bus connector Thus the follo...

Page 22: ...AKE PROCEDURE I th h d h k g in nd I all bus S gnals I i sI w liC the detecting the Bus free 1 M MC I I Of h h S I the REG ACK I I no la s I I data bus I Phase the Initiator I T ein L The Target first...

Page 23: ...The minimum time required for deskew of certain signals RESET HOLD TIME 25 microseconds The minimum time for which RST is asserted There is no maximum time SELECTION ABORT TIME 200 microseconds The ma...

Page 24: ...shows the drive startup current profile The wait Spin shorting plug option can be used to delay startup until the host issues SCSI START STOP UNIT commands thereby limiting the surge current when sta...

Page 25: ...which device wins arbitration if several devices are contending for the SCSI bus simultaneously Highest pri ority is address 7 usually given to the host and lowest priority is address o The three plug...

Page 26: ...r Locations wait Spin Option WS When the WS shorting plug is installed the motor waits for a START STOP UNIT command from the host via the SCSI bus before spinning Multiple drives can then be started...

Page 27: ...except wait Spin and goes to the SCSI bus free phase Unrecoverable read errors may result if a drive is cold reset while writing Cold reset typically takes six seconds during which time the drive can...

Page 28: ...o Amplifies read signals from each head about 100 times o Detects fault conditions such as defective heads write current while reading no write current and write data transitions too infrequent If fau...

Page 29: ...now follows controlled by the microprocessor which has been triggered by an interrupt from the 5080 At the start of a warm reset flip flop U29 Q pin 9 is toggled on by RESET CAP U29 then deasserts th...

Page 30: ...r A 5080 SCSI Controller IC is used to implement the SCSI interface CMOS technology reduces the power consumption All inputs and outputs conform to standard 5 V logic levels The SCSI bus pins of the 5...

Page 31: ...O HOST REGISTER STROBE HOST TO DMA REGISTER STROBE 1 S I YI r BUFFERED llATA BUS DMA CmHROL TO FROM DICE ONTROLLER TTL INPUT MADO 7 ADORESS DATA BUS 1 0 REG 5 STROBE HOST DATA REG 6 7 STROBE SELECT SE...

Page 32: ...shows the disk format including details of the servo signals in the wedges Seeking While a drive is seeking the read circuit reads the servo track numbers from the data in the servo bursts thus determ...

Page 33: ...me forces on the actuator from bearings windage the flex circuit gravity in some orientations and to compensate for any offset in the actuator circuitry NULL I is measured by changing the value in sma...

Page 34: ...F J H NJ K I I J QUAL ERR ____________ v o ADC RD MAD BUS 0 7 A B C 0 E F G 400ns H 4 200us 1 9 067us J B BOOus K 1 333us L 733ns M 533ns N 6 200us 0 933ns 2 600us P 600ns min 600ns Q 70ns max i 333u...

Page 35: ...inversely pro portional to the charge on C72 and thus to the burst amplitude When FYLO asserts CONVERT the AMC DAC converts this voltage to an 8 bit number The microprocessor places it on the MAD bus...

Page 36: ...through the actuator coil a differential current that is proportional to the out put of the error amplifier U5 senses the current as the difference voltage across R42 and R43 amplifies it by four and...

Page 37: ...l that exceed the level set by VHYS Qualified zero crossings trigger a one shot producing a pulse for each signal peak This is the output signal RAW DATA C7 sets the pulse width and R1 Cl set the dif...

Page 38: ...r U20 contains six non inverting buffers used to improve signal immunity to noise the inputs are 1A 6A the corresponding outputs are 1Y 6Y write current in the head is proportional to the current from...

Page 39: ...r module with driver ICs in a metal can at U25 AND gate pins 3 6 in U23 is required only for option 1 2 3 9 DICEY Data Controller IC DICEY is a custom data controller IC a 100 pin device proprietary t...

Page 40: ...lternating field of Is and Os o Detects sync pattern 100100 and generates a sync error if there is a drop out drop in or shifted bit o Controls access to buffer RAM via DMA transfers in this priority...

Page 41: ...isCache Microprocessor Data RAM Buffer RAM Buffer No 8031 128 X 8 16 Kbytes 14 KBytes Yes 8032 256 X 8 64 Kbytes 60 KBytes The Internal data RAM is used for look up tables that require fast access Com...

Page 42: ...0 Series Programmers Manual The READ command contains the starting logical block address and the transfer length in blocks Before reading each sector the Q250jQ280 checks the defect list and seeks to...

Page 43: ...SERVO BURST SEEK TO CYLINDER O HEAD 0 MEASURE SERVO BURST AMPL ITUOES ALL HEADS SEEK TO MID CYLINDER HEAD O MEASURE SERVO BURST AMPLITUDES ALL HEADS CALCULATE ADAPTIVE PARAMETERS KA NULL I AGC READ D...

Page 44: ...SK PULLED INTO TO BUFFER B031 RAM DECODE READ COMMAND DICEY BEGINS Y START TRANSFER CHECK ERROR SEEK FROM BUFFER PAGE FOR TO SCSI OPTIONS CHECK CHECK ACT PER DEFECT DEFECT OPTIONS LIST LIST RETRY CORR...

Page 45: ...FINO SECToR l Figure 2 17 write Command Sequence 2 36 A...

Page 46: ...s Locations PCB 7 Figure 3 2 Schematic PCB 7 Sheet 1 Figure 3 3 Schematic PCB 7 Sheet 2 Figure 3 4 Schematic PCB 7 Sheet 3 PCB 8 Engineering Drawings Figure 3 5 Printed Circuit Board Parts Locations P...

Page 47: ...C68 CJ WiD C54 1 QUANTUM CORP Q200 PCB 7 FAB 10 22007 SILKSCREEN ARTWORK 30 22007 REV 02 CRD A026 4 4 86 KRL or 5 J Ii CSO CSi R5 lit R5 III II i 1I f U Ril Figure 3 1 Printed Circuit Board Parts Loca...

Page 48: ...27 GND 3R 2B GND 3R r 29 GND 3R 30 GND 3R 31 GND 3R 32 ATN 3R ____ po _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 33 GND 3R 34 GND 3R 35 GND 3R 36 BSY 3R 37 GND 3R 3B ACK 3R 39 GND 3R 40 RST 3R 41 GND 3R 4...

Page 49: ...__ OA C CS _1 r_ i II CSOA 832 __ WR ____ _r i lr I B WRI 7406 5V P7WR2 _ R EA O GA o T E__ t ______ 9 _l 8 R12 12V XFER U7 3 55K k REF VREF R73 R79 1 1 1 18 10 R3 9 5 SK 1 2K y m _ ____f __ _ _ ___1...

Page 50: ...MAACK ATN 5 t j B SV _ c3 D J J 3 J 1L Z 7 A I 0 3 mD fQ B5 lY 1 t TT g 98 RDDATA UuXx J rc ___ ___________ 1 DMAIO AST 4 8 f4 M SG QD _ 1 j4 25 4 l r c t t r I1 J c _ I L _ 1 5 0 6 i 8K __ m I _ l C...

Page 51: ...a E F1 UlS III Ul u UtO 1 Ul cJ L O 1 CS9 D Q R99 os Q 0 70 J a o fi _ R3 RlO _ 6 R15 L1C o B c JQ2o 1 81 c ir D QL2i d C56 _ _ e _ N u D _ I J _ ij Ir 1 1 U D U I J m _u R64 w _RZ3TP2 TPt Lit c s _...

Page 52: ..._ 3R lL GND 03 5 V RTN 03 FIL 12 V _ 3R 29 GND 3R 04 5 V DC IL 04 GNO 3R 30 GNO 3R 05 BUF WR DATA _ 3R 31 GNO 3R 06 WR UNSAFE 3R 32 ATN 3R 07 GNO 3R 33 GND 3R 08 FIL 5 V _ __ 3R 34 GND 3R REF PIN SIGN...

Page 53: ...C TL O A C__ _I_ t ILE U3 20K 200K LM358A __ DA C CS _ i ______ _ _ _ ________ __ ____ _ _ t t _ t AC0832 EL2017 141 I I NPN D C62 Cc S I _ _ t 14 0022 m PNP IB U35 100 VOUT f 1 6 NPN __ WRL_____jlf_...

Page 54: ......

Page 55: ...LH 1 1 lJ40 E 14 R58 U3 LH R89 U C 1 I O 5 tD I 5 CS4 E13 csa CE9 I LJ I Ull I R 4 I I I I I U15 U14 C3J I I I I I n ID U O l I U T 3 R70 C 09 5 I 5 15 R3 C12 a _ D TP2 lFl LH R23 8 ICE I R 4 _ u U 8...

Page 56: ...D JR 35 GND 3R 36 8SY 3R f 3 7 t GN D iR _ _ _ 38 ACK 3R r i 39 GNO 3R _ _ _ _ _ 40 AST 3R 41 G fio jA 42 MSG 43 GND 44 SEL f r 3A JR jFi 45 GND JA 46 C O JR r r 47 GND 3A 48 REG 3R 49 GND JR r 5 0 I...

Page 57: ......

Page 58: ...D ACK p 4 7 5 f t CA CK _ J3 8 VIN INT WR GATE 6 _ _ _ OMACLK RST 4B RI03 RST _ WEDGE 1 GUAL ERR 1 _ _ t 22 PREVLO t_H _ _ t l2 15MHzCK 5V U29 74LSI12A _ _ _f 9 6 J lOR UNSAFE 4 2 ROCLK2 2 3 J ___ _ _...

Page 59: ...1 25 MByte sec Transfer Rate Here the initiator asserts ACK as soon as the data is latched and begins its DMA cycle When the target Q250 Q280 observes ACK asserted it deasserts REQ to inform the init...

Page 60: ...Ons 1 HOST LATCHES ACK 1 25 MBYTE SEC TRANSFER RATE CSI VALID DATA VALID TARGET DATA I REG I INITIATO INIT HAS LATCHED SCSI DATA MORE THAN 100ns DELAY J DISK CYCLE NOP CYCLE 1600ns SCSI CYCLE HOST DEL...

Page 61: ...e risk of receiving an invalid MESSAGE from devices other than Q200 Series drives 2 Set the Buffer Full Ratio and Buffer Empty Ratio see the Q200 Series Programmers Manual for details to improve bus u...

Page 62: ...ve is emptying it If the drive must seek the SCSI bus may fill the buf fer at which time the drive disconnects Now assume that the SCSI bus is much faster than the drive then the drive should reconnec...

Page 63: ...d Any discrepancy between recorded data and recovered data is defined as a data error Errors are either soft those not readily repeatable or hard those repeatable with high probability Soft errors are...

Page 64: ...if ECC correction is enabled 4 2 2 Allocating Replacement Sectors Traditionally replacement sectors are put in a reserved area of the drive far from the inside or outside diameter of the disk Thus wh...

Page 65: ...X deallocated sector x 30 x 61 x 189 spare Figure 4 3 In Line Sparing of Defective Sectors x x 32 x 61 x 157 x 1 x 2 x 29 Bad x 33 Bad XXXX XXXX x 186 x logical block address of initial sector Q280 cy...

Page 66: ...ctors Sectors at Factory Q250 823 103 698 1 646 50 Q280 823 156 370 1 646 80 4 2 3 creating the Defect Lists Defect lists map the defective sectors The lists are written on a system reserved cylinder...

Page 67: ...Updating the Drive Using the Defect Lists At any time during normal operation the user can choose to o Map out the defective blocks The user can submit aD list of defects and uses the REASSIGN BLOCKS...

Page 68: ...ble if o Electrostatic discharges occur for example by personnel touching the drive after walking over a carpet These may cause soft random non repeating errors but discharges over 20 kilovolts may ca...

Page 69: ...me is required for the AIRLOCK to lock the headstack assembly in the landing zone Level 1 Maintenance Replacement of the entire drive Replacement of plug in EPROM on printed circuit board PCB CAUTION...

Page 70: ...moistened with a contact cleaning solvent 5 5 PCB Waveforms and Techniques The waveforms described in this section may be observed for trouble shooting to determine if the PCB is operating correctly...

Page 71: ...If either of these signals is shorted to ground or another signal the drive may write over and destroy data and servo tracks Some of the signals can be observed at J5 the test connector where there is...

Page 72: ...e pulse for each transition of RDX and RDY 5 ENCODED DATA Observe at pin 4 of U9 or pin 13 of J5 ENCODED DATA is the output of FYLO and is the same as RAW DATA 6 READ DATA Observe this at the same tim...

Page 73: ...ge for U2 B See section 2 3 5 and section 2 3 7 See AMC Circuit in section 5 5 2 and Figure 5 3 1 2 V dc This voltage is changed in factory test to check the drive s margin 0 2 V dc This voltage is ch...

Page 74: ...Figure 5 1 Test Waveforms l TOP RAW DATA 1 Vjdiv BOTTOM RD DATA 1 Vjdiv 5 6...

Page 75: ...Figure 5 2 Test Waveforms 2 TOP RDX RDY Differential 5 mV div BOTTOM WEDGE 5 V div 5 7...

Page 76: ...Figure 5 3 Test Waveforms 3 TOP READ SIG READ SIG Differential 100 mv div BOTTOM BURST PEAK 1 V div 5 8...

Page 77: ...this is a very limited list For a complete list of PCB components refer to section 6 2 Part Number Description 20 22007 PCB 7 standard 20 22017 PCB 7 standard with warm reset rework 20 22027 PCB 7 st...

Page 78: ...respond to the PCB layouts Parts Loca tions illustrations provided in section 3 As in section 3 several iterations of the Q200 Series PCB are detailed in these lists Spec ifically the most current rev...

Page 79: ...a Ouantum Quantum Corporation 1804 McCarthy Blvd Milpitas CA 95035...

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