Qorvo PAC5556 User Manual Download Page 17

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Power Application Controller

-17-

2020 Qorvo, Inc.

Rev 2.2

– Nov 25, 2020

Figure 5-2 Analog Peripheral Register Write Timing

5.6

Read Register Example

To read the contents of the

HPDACH

▪

Write

SSPADAT

with the value 22h (11h << 1 | 0b for read transaction)

▪

Write

SSPADAT

with a dummy character

▪

Read last data from MISO from

SSPADAT

, this is the register value

The timing diagram from a read operation is shown below.

Figure 5-3 Analog Peripheral Register Read Timing

For more information on how to configure the DPM to support the USART A peripheral for
communicating with the Analog Registers, see the PAC55XX Family User Guide.

Summary of Contents for PAC5556

Page 1: ...on Controller 1 Copyright 2020 Qorvo Inc Rev 2 2 Nov 25 2020 PAC5556 Device User Guide Power Application Controller Configurable Analog Front EndTM Application Specific Power DriversTM Arm Cortex M4F...

Page 2: ...erview 15 5 2 Functional Description 15 5 3 USART Configuration 16 5 4 Protocol 16 5 5 Write Register Example 16 5 6 Read Register Example 17 6 PAC5556 IO 18 6 1 Overview 18 6 2 ADC Channels 19 6 3 Di...

Page 3: ...tem Block Diagram 42 10 3 Functional Description 43 10 4 Enabling the CAFE 43 10 5 Entering Hibernate Mode 43 10 6 Hibernate wake up using the Wake Up Timer 43 10 7 Hibernate wake up using Push Button...

Page 4: ...Amplifier Mode 68 10 14 4 AIO7 Comparator Mode 68 10 14 5 AIO7 Special Mode 69 10 15 AIO8 72 10 15 1 System Block Diagram 73 10 15 2 AIO8 Digital I O Mode 74 10 15 3 AIO8 Amplifier Mode 74 10 15 4 AI...

Page 5: ...2 98 10 18 18 SOC PROTINTEN 99 10 18 19 SOC PROTSTAT 100 10 18 20 SOC DOUTSIG0 101 10 18 21 SOC DOUTSIG1 101 10 18 22 SOC DINSIG0 102 10 18 23 SOC DINSIG1 102 10 18 24 SOC CFGIO1 103 10 18 25 SOC SIGI...

Page 6: ...Boot strap Pre Charge 118 11 10 Low side Gate Driver Short Protection 118 11 11 VP UVLO Configuration 118 11 12 Register Summary 119 11 13 Register Detail 120 11 13 1 SOC CFGDRV1 120 11 13 2 SOC CFGDR...

Page 7: ...22 Figure 8 1 EMUX Timing Diagram 28 Figure 9 1 CPM System Block Diagram 29 Figure 10 1 CAFE System Block Diagram 42 Figure 10 2 AIO10 Block Diagram 47 Figure 10 3 AIO32 Block Diagram 52 Figure 10 4...

Page 8: ...6 1 PAC5556 ADC Input Pins 19 Table 6 2 PAC5556 Digital Peripheral Pins 20 Table 7 1 PAC5556 ADC MUX channels 23 Table 7 2 PAC5556 ADC MUX channels 25 Table 7 3 PAC5556 ADC MUX channels 26 Table 9 1...

Page 9: ...Setting 12h 96 Register 10 14 SOC LPDACH LPDAC High Setting 13h 96 Register 10 15 SOC LPDAC1 LPDAC Low Setting 14h 96 Register 10 16 SOC SHCFG1 Sample and Hold Configuration 15h 97 Register 10 17 SOC...

Page 10: ...v 25 2020 Register 11 4 SOC STATDRV Driver Status 2Ah 123 Register 11 5 SOC CFGDRV4 Driver Configuration 4 7Bh 124 Register 11 6 SOC DRV_FLT Driver Fault Flag 7Ch 124 Register 11 7 SOC ENDRV Driver Ma...

Page 11: ...c Rev 2 2 Nov 25 2020 1 OVERVIEW This document is the PAC5556 Device User Guide It details the operation of the analog peripherals in the PAC5556 For detailed information on the MCU and Digital Periph...

Page 12: ...l 2 2 Formatting Styles TYPE EXAMPLE DESCRIPTION Register Name RTCCTL Register names use a capital letter and boldface type Register Bit s RTCCTL RTCCLKDIV Register bits are always represented with th...

Page 13: ...ARM CORTEX M4F CORE TIMERS 4 DEAD TIME 16 PWM CC 32 PWM ENGINE PX Y PX Y PX Y PX Y PX Y BRIDGE WWDT DTSE DATA ACQUISITION AND SEQUENCER 12 BIT ADC MUX PAC SOC BUS 3 x 1kB FLASH CONFIGURABLE POWER MANA...

Page 15: ...s the MCU and Debug Port access to FLASH and SRAM via the Memory Controller To access other digital peripheral connected to the APB bus there is a bridge from the AHB to the APB bus so that the MCU or...

Page 16: ...low When communicating with the Analog Peripherals the maximum SCLK frequency is 25MHz 5 4 Protocol The protocol for communicating with the Analog Peripherals is a simple two byte protocol The first b...

Page 17: ...RT A Write SSPADAT with the value 22h 11h 1 0b for read transaction Write SSPADAT with a dummy character Read last data from MISO from SSPADAT this is the register value The timing diagram from a read...

Page 18: ...er consider the available IO pins to make sure the necessary peripherals will be available Below is a diagram of the GPIO and MUX structure Figure 6 1 GPIO and DPM Block Diagram Each IO can be configu...

Page 19: ...2 2 Nov 25 2020 6 2 ADC Channels The ADC channels that are available on the PAC5556 are shown in the table below Table 6 1 PAC5556 ADC Input Pins ADC Channel IO PIN ADC0 PG71 ADC4 PF4 ADC5 PF5 ADC6 PF...

Page 20: ...OSI USCSCLK CANRXD I2CSCL P5 GPIOC5 TBPWM5 TCPWM5 TCQEPPHA USBMISO USCSS CANTXD I2CSDA P6 GPIOC6 TBPWM6 TCPWM6 TCQEPPHB USBSCLK USCMOSI EMUXD GPIOE P0 GPIOE0 TCPWM4 TDPWM0 TAIDX TBIDX USCSCLK I2CSCL E...

Page 21: ...ev 2 2 Nov 25 2020 P5 GPIOF5 TCPWM5 TDPWM5 TCPHA USDSS EMUXD P6 GPIOF6 TCPWM6 TDPWM6 TCPHB USDMOSI CANRXD I2CSCL P7 GPIOF7 TCPWM7 TDPWM7 USDMISO CANTXD I2CSDA For more information on how to configure...

Page 22: ...s MUXes that are used for signal sampling are shown in the diagram below Figure 7 1 PAC5556 ADC MUX inputs AFE MUX MCU 12 bit ADC PWRMON MUX VCORE DAO10 DAO32 DAO54 AB1 AB2 AB9 AB10 VPTAT AB12 VP x 1...

Page 23: ...556 ADC MUX channels ADC Channel MCU I O PIN Description ADC0 PG7 Connected to AFE MUX ADC4 PF4 Device pin ADC5 PF5 Device pin ADC6 PF6 Device pin ADC7 PF7 Device pin The ADC0 channel is always used f...

Page 24: ...registers set SOC SHCFG1 EMUXEN to 0b disabled The MUX channel may be selected from SOC SHCFG2 MUXA When the ADC is configured for DTSE mode the EMUX enable function in the AFE should be enabled To s...

Page 25: ...1010b Analog bus AB8 AB9 1011b Analog bus AB9 AB10 VPTAT 1100b Internal temperature sensor VPTAT AB11 PWRMON 1101b Power Monitor MUX input AB12 VP 10 1110b VP voltage 10 AB13 VREF 2 1111b VREF 2 For m...

Page 26: ...N Description VCORE 000b VCORE LDO output voltage VP x 1 10 001b VP MVBB output voltage scaled by 1 10 VCC33 x 4 10 010b VCC33 LDO output voltage scaled by 4 10 VCCIO x 4 10 011b VCCIO LDO output volt...

Page 27: ...nd hold engine POS BEMF sample and hold engine The format of the EMUX command used to control the AFE MUX is the same as is shown in SOC SHCFG2 The EMUX data is transmitted MSB first BIT NAME DESCRIPT...

Page 28: ...dge of the 1st clock cycle The AIO10 AIO32 and AIO54 sample and hold circuits are toggled based on the HLD 2 0 bits with the falling edge of the 4th clock cycle The AFE MUX select is switched with the...

Page 29: ...hibernate mode IQ of 8 A 9 2 System Block Diagram Figure 9 1 CPM System Block Diagram CONFIGURABLE POWER MANAGER VP VOLTAGE SETTING POWER OK OVP VSYS LINEAR REG LINEAR REG LINEAR REG VCCIO VCORE VCC33...

Page 30: ...supply regulator input and is connected to the rectified DC motor voltage source The BST and SRC pins are connected to the boot strap and source nodes of the power supply respectively The BST_CHG pin...

Page 31: ...ter the fault Table 1 1 Power Manager Fault Handling FAULT FAULT ENABLE ACTION FAULT BIT VP SOC FAULTENABLE VPFLTEN Disable VP VSYS VCCIO VCORE VCC18 and VCC33 SOC FAULT VPFLT VSYS SOC FAULTENABLE VSY...

Page 32: ...rrupt on IRQ1 will be asserted to the MCU Writing SOC FAULT TMPWARN_LATCH to 1b will reset this bit to 0b and will de assert the IRQ1 signal During this condition when the temperature falls below 125...

Page 33: ...T Fault condition indication register 00h 01h SOC STATUS Hardware status condition register 00h 02h SOC MISC Miscellaneous features register 00h 03h SOC PWRCTL Power Manager control register 00h 04h S...

Page 34: ...nd the IRQ1 signal write this bit to 1b 0b No temperature warning 1b Temperature warning 5 TMPFLT R 0x0 Temperature fault status If the temperature reaches the fault threshold this bit is set to 1b Wr...

Page 35: ...erved 3 VPLOW R 0x0 Real time VP Low Status 0b No VP low 1b VP low 2 VPLOW_LATCH R 0x0 Latched VP Low Status During VP low condition this bit is set and the IRQ1 signal is asserted To clear this bit a...

Page 36: ...nate push button wake up When this bit is set to 1b the internal pull up on AIO6 push button is enabled 0b Push button wake up not enabled 1b Push button wake up enabled 5 4 RFU R 0x0 Reserved write a...

Page 37: ...R 0x0 Reserved write as 00b 5 3 PWRMON R W 0x0 Power Monitor Signal This field selects the signal to use for AB11 for the PWRMON MUX 000b VCORE 001b VCORE x 4 10 010b VCC33 x 4 10 011b VCCIO x 4 10 10...

Page 38: ...arning Enable 0b Not enabled 1b Enabled 5 VPFLTEN R W 0x0 VP Fault Enable HV BUCK 0b Not enabled 1b Enabled 4 VSYSFLTEN R W 0x0 VSYS Fault Enable MV BUCK 0b Not enabled 1b Enabled 3 RFU R 0x0 Reserved...

Page 39: ...system soft reset This bit is always read as 0b When set the STATUS SRST bit will be latched to a 1b so the MCU knows the system is being started after a soft reset 0b Do not issue soft reset 1b Issue...

Page 40: ...SCONF System Configuration 2Bh BIT NAME ACCESS RESET DESCRIPTION 7 4 RFU R 0x0 Reserved write as 0x0 3 VPSET R W 0x1 HV BUCK VP Output Setting 0b 12V 1b 15V 2 0 HVBK_FREQ R W 100b HV BUCK Switching Fr...

Page 41: ...ode I O mode special mode 3 High Performance Configurable Differential Amplifiers 4 High Performance Configurable Single Ended Amplifiers Two high speed comparators with protection functions Phase to...

Page 42: ...MPx LP DAC HP DAC DIFF PGA PCOMP MUX OFFSET CAL PROTECT IRQ1 PR AFE MUX DAxN ADC MUX VTEMP VMON VREF VM CONFIGURABLE ANALOG SIGNAL MATRIX AMPx PGA MUX MUX BUF6 COMPARATOR MUX DINx CONFIGURABLE ANALOG...

Page 43: ...ations A push button function is provided for optional push button on hibernate and off power management function 10 4 Enabling the CAFE Before the CAFE sub system can be begin any signal conditioning...

Page 44: ...ing time used for the push button detection Before entering hibernate mode set the de bouncing time by setting SOC MISC TPBD to 0b 32ms or 1b 1ms After the de bouncing time has expired and the push bu...

Page 47: ...CFGAIO0 MUX0 CFGAIO1 OPT1 CFGAIO0 MODE10 CFGAIO1 POL1 I O Logic Polarity OD MUX DINSIG0 DIN1 DOUTSIG0 DOUT1 I O CFGAIO1 MUX1 DBUS DBx AIO10 Protection LPDACH LPDACL CFGAIO0 LP10EN CFGAIO0 LP10PREN Pro...

Page 48: ...be read at SOC DINSIG0 DIN1 Set SOC CFGAIO1 OPT1 10b to use AIO1 as open drain output Set SOC CFGAIO1 MUX1 00b to mux the output state from SOC DOUTSIG0 DOUT1 Use SOC CFGAIO1 MUX1 to mux the output si...

Page 49: ...D0 to a 0b release The AFE MUX channel may be selected by writing SOC SHCFG2 MUXA to the desired channel When the ADC is in automatic mode ADC sequencer active the sample and hold state as well as the...

Page 50: ...GAIO0 LP10EN may be used to enable LP10 comparator with different blanking times Set SOC SIGSET LPROTHYS to 1b to enable LP10 comparator hysteresis The output of LP10 comparator can be configured to t...

Page 52: ...UT2 I O CFGAIO2 MUX2 CFGAIO3 OPT3 CFGAIO2 MODE32 CFGAIO3 POL3 I O Logic Polarity OD MUX DINSIG0 DIN3 DOUTSIG0 DOUT3 I O CFGAIO3 MUX3 DBUS DBx AIO32 Protection LPDACH LPDACL CFGAIO2 LP32PREN Protection...

Page 53: ...or output polarity of AIO3 use SOC CFGAIO3 POL3 to set logic polarity of the signal between AIO3 input output and MUX3 10 11 3 AIO3 AIO2 Differential Amplifier Mode To configure AIO32 as a differentia...

Page 54: ...ide comparator protector LP32 are also active that can be configured to disable high side or low side gate drivers in the Application Specific Power Driver ASPD 10 11 3 3 HP32 Comparator The HP32 comp...

Page 55: ...Rev 2 2 Nov 25 2020 The output of LP32 can also trigger the IRQ1 interrupt by setting SOC PROTINTEN LP32INTEN to 1b The real time status can be observed using SOC SIGINTEN LP32STAT and the latched int...

Page 57: ...CFGAIO4 MUX4 CFGAIO5 OPT5 CFGAIO4 MODE54 CFGAIO5 POL5 I O Logic Polarity OD MUX DINSIG0 DIN5 DOUTSIG0 DOUT5 I O CFGAIO5 MUX5 DBUS DBx AIO54 Protection LPDACH LPDACL CFGAIO4 LP54EN CFGAIO4 LP54PREN Pro...

Page 58: ...or output polarity of AIO5 use SOC CFGAIO5 POL5 to set logic polarity of the signal between AIO5 input output and MUX5 10 12 3 AIO4 AIO5 Differential Amplifier Mode To configure AIO54 as a differentia...

Page 59: ...ide comparator protector LP54 are also active that can be configured to disable high side or low side gate drivers in the Application Specific Power Driver ASPD 10 12 3 3 HP54 Comparator The HP54 comp...

Page 60: ...Rev 2 2 Nov 25 2020 The output of LP54 can also trigger the IRQ1 interrupt by setting SOC PROTINTEN LP54INTEN to 1b The real time status can be observed using SOC PROTSTAT LP54STAT and the latched int...

Page 61: ...t 2020 Qorvo Inc Rev 2 2 Nov 25 2020 10 13 AIO6 AIO6 may be configured as a digital input single ended programmable gain amplifier comparator output from analog ABUS or as a push button input to wake...

Page 62: ...6 AIO6 CFGAIO6 MODE6 AIO6 Amplifier VSSA ABx ABUS MUX CFGAIO6 MUX6 CFGAIO6 GAIN6 CMP CFGAIO6 MODE6 AIO6 Comparator DBx DBUS ABUS MUX AB 3 1 DOUTSIG0 VTHREF VTHREF MUX CFGAIO6 POL6 CMP Polarity CFGAIO6...

Page 63: ...cted an interrupt will be asserted on IRQ2 to the MCU The interrupt status can be monitored by reading SOC SIGINTEN AIO6INT and cleared by writing SOC SIGINTEN AIO6INTF to 1b 10 13 3 AIO6 Amplifier Mo...

Page 64: ...IGINTEN AIO6INTF to 1b In this mode AIO6 may also be used to detect an over current event and to notify the ASPD to disable the gate drivers much like the differential amplifier mode To signal the ASP...

Page 65: ...ication Controller 65 Copyright 2020 Qorvo Inc Rev 2 2 Nov 25 2020 10 14 AIO7 AIO7 may be configured as a digital input output single ended programmable gain amplifier comparator or a BEMF zero cross...

Page 67: ...THREF MUX CFGAIO7 POL7 CMP Polarity CFGAIO7 MUX7 CFGAIO7 OPT7 DINSIG1 DIN7 Input SIGINTF AIO7INT SIGINTEN AIO7REINTEN SIGINTEN AIO7FEINTEN BLANKING BLANKMODE SPECCFG0 AIO7HYS SPECCFG0 HYSMODE SPECCFG2...

Page 68: ...When the edge is detected an interrupt will be asserted on IRQ2 to the MCU The interrupt status can be monitored by reading SOC SIGINTEN AIO7INT and cleared by writing SOC SIGINTEN AIO7INTF to 1b 10...

Page 69: ...active low The output of the comparator may be sent to the digital bus DB1 to DB7 or to SOC DINSIG1 DIN7 by using SOC CFGAIO7 MUX7 10 14 4 3 I O and Interrupts In this mode the digital input state an...

Page 70: ...ING BLANKMODE is not 00b disabled then the blanking time may be configured to be between 100ns and 6000ns by setting the value in SOC BLANKING BLANKTIME The comparator hysteresis may be configured ind...

Page 71: ...O7 voltage from the AFE MUX The BEMF position output POS can be selected between AIO 9 7 through the MUX at the output of the comparator polarity selector To select the output of the AIO7 comparator f...

Page 72: ...pplication Controller 72 Copyright 2020 Qorvo Inc Rev 2 2 Nov 25 2020 10 15 AIO8 AIO8 may be configured as a digital input single ended programmable gain amplifier comparator or a BEMF zero cross comp...

Page 73: ...ABUS MUX AB 3 1 DOUTSIG0 VTHREF VTHREF MUX CFGAIO8 POL8 CMP Polarity CFGAIO8 MUX8 CFGAIO8 OPT8 DINSIG1 DIN8 Input SIGINTF AIO8INT SIGINTEN AIO8REINTEN SIGINTEN AIO8FEINTEN BLANKING BLANKMODE SPECCFG1...

Page 74: ...b When the edge is detected an interrupt will be asserted on IRQ2 to the MCU The interrupt status can be monitored by reading SOC SIGINTEN AIO8INT and cleared by writing SOC SIGINTEN AIO8INTF to 1b 10...

Page 75: ...active low The output of the comparator may be sent to the digital bus DB1 to DB7 or to SOC DINSIG1 DIN8 by using SOC CFGAIO8 MUX8 10 15 5 2 I O and Interrupts In this mode the digital input state an...

Page 76: ...f SOC BLANKING BLANKMODE is not 00b disabled then the blanking time may be configured to be between 100ns and 6000ns by setting the value in b The comparator hysteresis may be configured independently...

Page 77: ...t AIO8 voltage from the AFE MUX The BEMF position POS can be selected between AIO 9 7 through the MUX at the output of the comparator polarity selector To select the output of the AIO8 comparator for...

Page 78: ...pplication Controller 78 Copyright 2020 Qorvo Inc Rev 2 2 Nov 25 2020 10 16 AIO9 AIO9 may be configured as a digital input single ended programmable gain amplifier comparator or a BEMF zero cross comp...

Page 79: ...DBUS ABUS MUX AB 3 1 DOUTSIG0 VTHREF VTHREF MUX CFGAIO9 POL9 CMP Polarity CFGAIO9 MUX9 CFGAIO9 OPT9 DINSIG1 DIN9 Input SIGINTF AIO9INT SIGINTEN AIO9REINTEN SIGINTEN AIO9FEINTEN BLANKING BLANKMODE SPEC...

Page 80: ...o 1b When the edge is detected an interrupt will be asserted on IRQ2 to the MCU The interrupt status can be monitored by reading SOC SIGINTEN AIO9INT and cleared by writing SOC SIGINTEN AIO9INTF to 1b...

Page 81: ...comparator hysteresis scale for AIO9 set SOC SPECCFG0 HYSMODE and to set the hysteresis level set SOC SPECCFG1 AIO9HYS The output polarity of the comparator may be selected by using SOC CFGAIO9 POL9...

Page 82: ...MUXAIO9 to select the comparator reference To select the VTHREF comparator threshold use SOC DOUTSIG0 VTHREF to select a value from the following 00b 0 1V 01b 0 2V 10b 0 5V 11b 1 25V 10 16 4 2 Compara...

Page 83: ...fier mode and SOC CFGAIO6 GAIN6 000b direct mode and SOC CFGAIO6 MUX6 001b output to AB1 To MUX the AIO9 voltage on AB9 with 40 attenuation set SOC CFGAIO9 MODE9 1 1b so the ADC can read out AIO9 volt...

Page 84: ...OC LPDACH Low Protection Threshold 0x00 0x14 SOC LPDACL Low Protection Threshold 0x00 0x15 SOC SHCFG1 Sample and Hold Configuration 1 0x00 0x16 SOC SHCFG2 Sample and Hold Configuration 2 0x00 0x17 SOC...

Page 85: ...Z GAIN10 Differential amplifier gain setting 000b 1x 010b 1x 011b 2x 001b 4x 100b 8x 101b 16x 110b 32x 111b 48x 3 POL0 RW 0b POL0 AIO0 Polarity If CFGAIO0 OPT0 00b AIO0 input polarity setting If CFGAI...

Page 86: ...EN LPROT10 PR Protection enable 0b LP10 output to PR disabled 1b LP10 output to PR enabled 3 POL1 RW 0b If CFGAIO1 OPT1 00b AIO1 input polarity setting If CFGAIO1 OPT1 10b AIO1 output polarity setting...

Page 87: ...GAIN32 Differential amplifier gain setting 000b 1x 010b 1x 011b 2x 001b 4x 100b 8x 101b 16x 110b 32x 111b 48x 3 POL2 RW 0b If CFGAIO2 OPT2 00b AIO2 input polarity setting If CFGAIO2 OPT2 10b AIO2 outp...

Page 88: ...EN LPROT32 PR Protection enable 0b LP32 output to PR disabled 1b LP32 output to PR enabled 3 POL3 RW 0b If CFGAIO3 OPT3 00b AIO3 input polarity setting If CFGAIO3 OPT3 10b AIO3 output polarity setting...

Page 89: ...b Hi Z GAIN54 Differential amplifier gain setting 000b 1x 010b 1x 011b 2x 001b 4x 100b 8x 101b 16x 110b 32x 111b 48x 3 POL4 RW 0b If CFGAIO4 OPT4 00b AIO4 input polarity setting If CFGAIO4 OPT4 10b AI...

Page 90: ...EN LPROT54 PR Protection enable 0b LP54 output to PR disabled 1b LP54 output to PR enabled 3 POL5 RW 0b If CFGAIO5 OPT5 00b AIO5 input polarity setting If CFGAIO5 OPT5 10b AIO5 output polarity setting...

Page 91: ...REF 01b AB1 10b AB2 11b AB3 ADMUX 1b Switch ADCIN to AB7 4 SWAP Buffer Swap 0b Do not swap buffer offset 1b Swap buffer offset 3 POL6 AIO6 Polarity Setting 00b active high 01b active low POL6 AIO6 Com...

Page 92: ...48x OPT7 AIO7 Comparator Reference select 00b VTHREF 01b AB1 10b AB2 11b AB3 Reserved write as 0b 4 Reserved write as 0b 3 POL7 AIO7 Polarity Setting 00b active high 01b active low POL7 AIO7 Comparat...

Page 93: ...11b AB3 OPT8 1 S H bypass for POS 0b Bypass S H for POS signal 1b Do not bypass S H for POS signal 4 OPT8 2 nIRQ2 POS output 0b Select IRQ2 POS output POS BEMF 1b Select IRQ2 POS output nIRQ2 INT 3 PO...

Page 94: ...00b VTHREF 01b AB1 10b AB2 11b AB3 OPT9 AIO789 comparator output to POS 00b not connected 01b MUX AIO7 comparator output to POS 10b MUX AIO8 comparator output to POS 11b MUX AIO9 comparator output to...

Page 95: ...HPROTHYS RW 0b HPx Hysteresis 0b Comparator Hysteresis disabled 1b Comparator Hysteresis enabled 2 LPROTHYS RW 0b LPx Hysteresis 0b Comparator Hysteresis disabled 1b Comparator Hysteresis enabled 1 L...

Page 96: ...DAC High Setting 13h 10 18 15 SOC LPDACL Register 10 15 SOC LPDAC1 LPDAC Low Setting 14h BIT NAME ACCESS RESET DESCRIPTION 7 0 HPDAC RW 0 HPDAC MSB setting bits 9 2 BIT NAME ACCESS RESET DESCRIPTION 7...

Page 97: ...b will reset the EMUX 1b Enabled 3 ADCBUFEN RW 0b ADCBUF Circuit Enable 0b Disabled 1b Enabled 2 DAO54SH RW 0b Enable sample and hold circuit to synchronize the Differential Amplifier 54 output to ADC...

Page 98: ...d this bit is always 0b 1b Hold POS value 6 HLD2 RW 0b DAO54 Sample and Hold Output 0b Sample 1b Hold 5 HLD1 RW 0b DAO32 Sample and Hold Output 0b Sample 1b Hold 4 HLD0 RW 0b DAO10 Sample and Hold Out...

Page 99: ...EN RW 0b HPROT54 Interrupt enable 0b Not enabled 1b Enabled 5 HP32INTEN RW 0b HPROT32 Interrupt enable 0b Not enabled 1b Enabled 4 HP10INTEN RW 0b HPROT10 Interrupt enable 0b Not enabled 1b Enabled 3...

Page 100: ...upt 1b Interrupt write 1b to clear 5 HP32INT RW 0b HPROT32 Interrupt 0b No interrupt 1b Interrupt write 1b to clear 4 HP10INT RW 0b HPROT10 Interrupt 0b No interrupt 1b Interrupt write 1b to clear 3 L...

Page 101: ...voltage for comparators in AIO 9 6 00b 0 1V 01b 0 2V 10b 0 5V 11b 1 25V 5 DOUT5 RW 0b Data output to AIO5 4 DOUT4 RW 0b Data output to AIO4 3 DOUT3 RW 0b Data output to AIO3 2 DOUT2 RW 0b Data output...

Page 102: ...o 0 5 DIN5 R 0b Data input from AIO5 4 DIN4 R 0b Data input from AIO4 3 DIN3 R 0b Data input from AIO3 2 DIN2 R 0b Data input from AIO2 1 DIN1 R 0b Data input from AIO1 0 DIN0 R 0b Data input from AIO...

Page 103: ...SOC CFGIO1 AIO10 AIO13 Configuration 1 1Dh BIT NAME ACCESS RESET DESCRIPTION 7 5 RFU R 000b Reserved write as 0 4 EN_AIO6_OCP RW 0b Enable AIO6 comparator output to disable gate driver on OC event 3...

Page 104: ...abled 1b enabled 5 AIO7REINTEN RW 0b AIO7 digital input rising edge interrupt enable 0b disabled 1b enabled 4 AIO6REINTEN RW 0b AIO6 digital input rising edge interrupt enable 0b disabled 1b enabled 3...

Page 105: ...ut high 5 HP10STAT R 0b HPROT10 Real time status 0b Comparator output low 1b Comparator output high 4 LP10STAT R 0b LPROT10 Real time status 0b Comparator output low 1b Comparator output high 3 AIO9IN...

Page 106: ...anking time for BEMF Comparator 0000b 100ns 0001b 250ns 0010b 500ns 0011b 750ns 0100b 1000ns 0101b 1250ns 0110b 1500ns 0111b 2000ns 1000b 2500ns 1001b 3000ns 1010b 3500ns 1011b 4000ns 1100b 4500ns 110...

Page 107: ...Falling 10mV 0111b Rising 5mV Falling 20mV 1000b Rising 10mV Falling 0mV 1001b Rising 10mV Falling 5mV 1010b Rising 10mV Falling 10mV 1011b Rising 10mV Falling 20mV 1100b Rising 20mV Falling 0mV 1101b...

Page 108: ...1 0000b Rising 0mV Falling 0mV 0001b Rising 0mV Falling 20mV 0010b Rising 0mV Falling 40mV 0011b Rising 0mV Falling 80mV 0100b Rising 20mV Falling 0mV 0101b Rising 20mV Falling 20mV 0110b Rising 20mV...

Page 109: ...sing 40mV Falling 20mV 1010b Rising 40mV Falling 40mV 1011b Rising 40mV Falling 80mV 1100b Rising 80mV Falling 0mV 1101b Rising 80mV Falling 20mV 1110b Rising 80mV Falling 40mV 1111b Rising 80mV Falli...

Page 110: ...UX Input Configuration 25h BIT NAME ACCESS RESET DESCRIPTION 7 RFU R 0b Reserved write to 0b 6 4 SMUXAIO9 RW 000b Special Mode Comparator Input MUX Selection for AIO7 000b VTHREF 001b AB1 virtual cent...

Page 111: ...Rev 2 2 Nov 25 2020 11 APPLICATION SPECIFIC POWER DRIVER 11 1 Features 3 high side gate drivers with 250mA sink and 500mA source current 3 low side gate drivers with 1A sink and 1A source current Fas...

Page 112: ...v 25 2020 11 2 System Block Diagram Figure 11 1 ASPD System Block Diagram APPLICATION SPECIFIC POWER DRIVERS HIGH SIDE GATE DRIVERS PRE DRIVER DXHx DXSx DXBx LEVEL SHIFT FAULT PROTECT CURRENT LIMIT HS...

Page 113: ...voltage high side gate drivers Figure 11 2 ASPD High Side Gate Drivers DXSx PRE DRIVER DXHx ENDRV SOC ENDRV ENDRV PC 6 4 CBCCTL SOC CFGDRV2 DRVxyDIS SOC CFGDRV3 HPCBCEN SOC STATDRV DRVxyDISSTAT SOC S...

Page 114: ...DISSTAT SOC STATDRV DRVxyDIS The ASPD contains 3 push pull low side gate drivers The DRL 2 0 outputs of the ASPD are used to drive the gate of an external low side power IGBT The supply for the low si...

Page 115: ...has a protection input signal PR that notifies the ASPD of a protection event If the ASPD has unmasked the high side PR protection SOC CFGDRV1 HSPREN 1b then the high side gate drivers will be disable...

Page 116: ...be used to generate an event signal PWMCBC which can be used to control this operation Figure 11 4 Cycle by Cycle Current Limit The mask signal SOC CFGDRV2 DRVxyDIS is used to select which half bridge...

Page 117: ...CFGDRV2 LPCBCLS 1b and SOC CFGDRV2 DRV52DIS 1b disable DRL2 PWMCBC high If SOC CFGDRV2 LPCBCHS 1b and SOC CFGDRV2 DRV41DIS 1b disable DXH1 If SOC CFGDRV2 LPCBCLS 1b and SOC CFGDRV2 DRV41DIS 1b disable...

Page 118: ...ver Short Protection The driver manager can detect short circuit conditions in the low side MOSFET when enabled To enable this feature set SOC ENDRV DRVFLTEN driver fault enable to 1b When the low sid...

Page 119: ...DESCRIPTION RESET 27h SOC CFGDRV1 Driver Configuration 1 00h 28h SOC CFGDRV2 Driver Configuration 2 00h 29h SOC CFGDRV3 Driver Configuration 3 00h 2Ah SOC STATDRV Driver Status 00h 7Bh SOC CFGDRV4 Dr...

Page 120: ...GDRV1 Register 11 1 SOC CFGDRV1 Driver Configuration 1 27h BIT NAME ACCESS RESET DESCRIPTION 7 4 RFU R 0x0 Reserved write as 0x0 3 HSPREN RW 0b High side PR protection enable 0b PR disabled 1b PR enab...

Page 121: ...DXH1 DRL1 high side low side or both Used for PWM pulse cycle by cycle current limit 0b do not assert disable signal 1b assert disable signal 2 DRV30DIS R W 0b Disable signal for DXH0 DRL0 high side l...

Page 122: ...M pulse cycle by cycle current limit 0b enabled 1b not enabled 5 HP32CBCM R W 0b Enable signal for HPROT32 for PWM pulse cycle by cycle current limit 0b enabled 1b not enabled 4 LP32CBCM R W 0b Enable...

Page 123: ...iver disable inactive 1b Driver disable active 3 DRV30DISSTAT R 0b Real time status of DRV30DIS signal 0b Driver disable inactive 1b Driver disable active 2 DRV52DIS R 0b Latched status of DRV54DIS si...

Page 124: ...rved write as 0x0 1 VPUVLOQUAL R W 0b VP UVLO Power OK qualify 0b VP UVLO determined by just VP threshold 1b VP UVLO determined by VP threshold and VP power OK threshold 0 PRECHARGE R W 0b Boot strap...

Page 125: ...ler 125 Copyright 2020 Qorvo Inc Rev 2 2 Nov 25 2020 11 13 8 SOC WDTPASS Register 11 8 SOC WDTPASS WDT Password 7Eh BIT NAME ACCESS RESET DESCRIPTION 7 0 WDTPASS R W 0x0 To reset the SOC Watchdog Time...

Page 126: ...i assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein Customers should evalua...

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