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ACT88326

Advanced PMU with Bypass Switch,

& Pushbutton Function

Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice

37 of 45

www.qorvo.com

(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches

Tél. 01 47 95 99 84 - Fax. 01 47 01 16 22 - e-mail: [email protected] - Site Web: www.es-france.com

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Summary of Contents for ACT88326

Page 1: ...the need for PCB changes The low external component count and high configurability significantly speeds time to market Examples of configurable options include output voltage startup time slew rate sy...

Page 2: ...YPICAL APPLICATION DIAGRAM LDO1 300mA BUCK1 4A BUCK2 3A BUCK3 3A LDO2 300mA SCL SDA nRESET IRQ PG External DC DC ENABLE 2 7V 5 5V Input PWREN SOC ACT88326 ES Equipements Scientifiques SA D partement C...

Page 3: ...s Controller Vref 22 F 1 H FB_B2 SW_B2 VIN FB_B2 10 F Buck3 Controller Vref 22 F 1 H FB_B3 SW_B3 VIN FB_B3 10 F nPB SDA GPIO1 GPIO2 EN PG GPIO4 GPIO3 Vref LDO1 Vref AVIN LDO2 Load Switch Gate Drives A...

Page 4: ...custom options minimum order quantity required Note 2 All Active Semi components are RoHS Compliant and with Pb free plating unless specified differently The term Pb free means semiconductor products...

Page 5: ...VIN_B2 VIN_B2 3 SW_B3 SW_B2 SW_B2 SW_B2 4 SW_B3 PGND12 PGND12 PGND12 5 PGND3 SW_B1 SW_B1 SW_B1 6 AGND GPIO3 GPIO2 VIN_B1 VIN_B1 VIN_B1 7 SDA SCL GPIO1 GPIO4 VIN_IO FB_B1 Figure 1 Pin Configuration To...

Page 6: ...ND12 Power Ground for Buck1 and Buck2 Connect the Buck1 and Buck2 input caps directly to these pins A5 PGND3 Power Ground for Buck3 Connect the Buck3 input caps directly to these pins D5 E5 F5 SW_B1 S...

Page 7: ...0 3 to VIN_xx 0 3 V AGND to PGND12 0 3 to 0 3 V Junction to Ambient Thermal Resistance Note 2 39 C W Junction to Case Thermal Resistance Note 2 6 5 C W Operating Junction Temperature 40 to 150 C Stor...

Page 8: ...nal resistor for Push button function AVIN 3 3V 50 k nPB external resistor for Manual Reset function AVIN 3 3V 1 k nPB internal pullup resistor AVIN 3 3V 0 6 2 M nPB Manual Reset MR rising threshold 0...

Page 9: ...1500 2000 s Oscillator Frequency 2 13 2 25 2 37 MHz VIN UV Interrupt Threshold Falling Referenced to rising threshold 200 mV VIN UV Threshold Rising Programming Range Rising edge threshold can power u...

Page 10: ...steps 0 7 75 ms nRESET Programmable Range Configurable to 20 40 60 or 100ms 20 100 ms Note 1 All Under voltage Lockout Overvoltage measurements are referenced to the AVIN Input and AGND Pins Note 2 A...

Page 11: ...Power Good Threshold VOUT_B1 Rising 90 92 5 95 VNOM Power Good Hysteresis VOUT_B1 Falling 3 VNOM Overvoltage Fault Threshold VOUT_B1 Rising 107 5 110 112 5 VNOM Overvoltage Fault Hysteresis VOUT_B1 F...

Page 12: ...0 06 Internal PMOS Current Detection Triggers Interrupt on IRQ Pin 2 8 4 2 5 4 A Internal PMOS Current Detection Deglitch Time 10 s Internal PMOS Current Shutdown Shuts down after deglitch time and st...

Page 13: ...egulation 0 1 Power Good Threshold VOUTx Rising 90 92 5 95 VNOM Power Good Hysteresis VOUTx Falling 3 VNOM Overvoltage Fault Threshold VOUTx Rising 107 5 110 112 5 VNOM Overvoltage Fault Hysteresis VO...

Page 14: ...DOx_OUT 1 8V Note 1 31 2 dB f 2 25MHz ILDOx_OUT 20mA VLDOx_OUT 1 8V Note 1 53 6 dB Supply Current per Output Regulator Disabled 1 A Supply Current Regulator Enabled No load 15 20 A Soft Start Period T...

Page 15: ...PMOS Current Shutdown Deglitch Time 5 s Internal PMOS Current Shutdown Off time Retry time 14 ms Internal PMOS Soft start Only used with 3 3V Input Cout 1uF Default Setting ISS 1 0 00 10 mV s LOAD SW...

Page 16: ...n 260 ns Capacitance on SCL or SDA Pin 10 pF SDA Fall Time SDA Tof Device requirement 120 ns Pulse Width of spikes must be suppressed on SCL and SDA 0 50 ns Note1 Comply with I2 C timings for 1MHz ope...

Page 17: ...e Address 8 Bit Read Address 0x25h 010 0101b 0x4Ah 0x4Bh 0x27h 010 0111b 0x4Eh 0x4Fh 0x67h 110 0111b 0xCEh 0xCFh 0x6Bh 110 1011b 0xD6h 0xD7h There is no timeout function in the I2C packet processing s...

Page 18: ...ACTIVE State The ACTIVE state is the normal operating state when the input voltage is within the allowable range all outputs are turned on and no faults are present The ACT88326 enters the ACTIVE stat...

Page 19: ...ion of these three inputs to enter DPSLP state The I2C bit DPSLP MODE is set at factory and cannot be changed by the user It controls the logical combination of the GPIO input and the DPSLP register b...

Page 20: ...lators when the user actively initiates a power on by either asserting nPB or by writing a 0 into the I2C POWER OFF bit When powering on with the nPB pin any fault that occurs before nPB is released t...

Page 21: ...e All buck converter softstart times are controlled by a single I2C bit ALL_BUCKS_FASTER_SS When set to 0 the softstart times are 600 s When set to 1 the softstart times are 250 s The default softstar...

Page 22: ...e fault flag bits display the real time fault status Their status is valid regardless of whether or not that fault is masked The mask bits either block or allow the fault to affect the fault bit Each...

Page 23: ...aults for which regulators mask the UV and OV fault conditions Output Current Limit The ACT88326 incorporates a three level overcurrent protection scheme for the buck converters and a single level sch...

Page 24: ...l outputs off and automatically restarts them Initiate Power Cycle1 by momentarily pulling nPB to ground through a 50k resistor for 4s When nPB transitions back high the IC transitions from its curren...

Page 25: ...the load switch FET gate drive pin LDOx These are the LDO output pins Each LDO output must be bypassed to AGND with a 1uF capacitor AGND AGND is the ground pin for the IC s analog circuitry and LDOs...

Page 26: ...nal rectifiers Soft Start Buck1 2 3 include internal 600us soft start ramps which limit the rate of change of the output voltage minimizing input inrush current and ensuring that the output powers up...

Page 27: ...ing or falling clock edge via the PHASE I2C bit Minimum On Time The ACT88326 minimum on time is approximately 125ns If a buck converter s calculated on time is less than 125ns with 2 25MHz operation t...

Page 28: ...rs utilize current mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating rang...

Page 29: ...ns Soft Start Each LDO contains a softstart circuit that limits the rate of change of the output voltage minimizing input inrush current and ensuring that the outputs power up monotonically This circu...

Page 30: ...high quality low ESR ceramic output capacitor A 1uF is typically suitable but this value can be increased without limit The input capacitor is should be a X5R X7R or similar dielectric The LDO effect...

Page 31: ...nput capacitor s pads Using 0805 sized input capacitors is recommended Avoid routing sensitive analog signals near these high frequency high dV dt traces 3 Place the LDO input capacitor close to the A...

Page 32: ...LSG VIN_B3 SW_B2 SW_B2 PGND PGND SW_B1 VIN_B1 VIN_B1 FB_B1 VIN_IO VIN_B1 GPIO2 VIN_B3 SW_B2 PGND SW_B1 GPIO3 PWREN LDO2 FB_B3 LDO1 GPIO4 SCL VIN_B2 SW_B3 SW_B3 PGND AGND SDA FB_B2 GPIO1 AVIN SW_B1 ES...

Page 33: ...019 Subject to change without notice 33 of 45 www qorvo com TYPICAL OPERATING CHARACTERISTICS ES Equipements Scientifiques SA D partement Composants Modules 127 rue de Buzenval BP 26 92380 Garches T l...

Page 34: ...Rev 3 0 Nov 11 2019 Subject to change without notice 34 of 45 www qorvo com ES Equipements Scientifiques SA D partement Composants Modules 127 rue de Buzenval BP 26 92380 Garches T l 01 47 95 99 84 F...

Page 35: ...Rev 3 0 Nov 11 2019 Subject to change without notice 35 of 45 www qorvo com ES Equipements Scientifiques SA D partement Composants Modules 127 rue de Buzenval BP 26 92380 Garches T l 01 47 95 99 84 F...

Page 36: ...Rev 3 0 Nov 11 2019 Subject to change without notice 36 of 45 www qorvo com ES Equipements Scientifiques SA D partement Composants Modules 127 rue de Buzenval BP 26 92380 Garches T l 01 47 95 99 84 F...

Page 37: ...Rev 3 0 Nov 11 2019 Subject to change without notice 37 of 45 www qorvo com ES Equipements Scientifiques SA D partement Composants Modules 127 rue de Buzenval BP 26 92380 Garches T l 01 47 95 99 84 F...

Page 38: ...uF 10V X5R Standard Input Capacitor LDO1 2 1uF 10V X5R Standard Output Capacitor Buck1 2x22uF 10V X5R Standard Output Capacitor Buck2 3 22uF 10V X5R Standard Output Capacitor LDO1 2 1uF 10V X5R Standa...

Page 39: ...d for the Ambarella H22 processor for use in video applications Voltage and Currents Rail Active Mode Voltage VSET0 V DVS Voltage VSET1 V DVS Input Trigger Sleep Mode Voltage V DPSLP Mode Voltage V Cu...

Page 40: ...hen Buck1 goes high After power up GPIO2 can be controlled via I2C to enable and disable the external power supply GPIO3 pin B6 nIRQ GPIO3 is configured as an open drain nIRQ output GPIO4 pin D7 nRESE...

Page 41: ...between 0 8V and 3 998V in 12 5mV steps Buck3 Voltage Setting Buck3 reference voltage is 0 8V This sets the allowable voltage range between 0 8V and 3 998V in 12 5mV steps LDO Voltage Setting LDO ref...

Page 42: ...LS1 outputs When GPIO1 is L these outputs are off When GPIO1 is H these outputs immediately turn on with no delay GPIO2 pin C6 EXT_PG2 GPIO2 is configured as a GPIO input to control the LDO1 and LDO2...

Page 43: ...8V in 12 5mV steps LDO Voltage Setting The LDO reference voltage is 0 6V This sets the allowable voltage range between 0 6V and 2 991V in 9 376mV steps Power Cycle1 EN_PB_PWRCYCL bit 1 This enables th...

Page 44: ...ange without notice 44 of 45 www qorvo com PACKAGE OUTLINE AND DIMENSIONS Top View Bottom View Side View Notes ES Equipements Scientifiques SA D partement Composants Modules 127 rue de Buzenval BP 26...

Page 45: ...ctual property rights whether with regard to such information itself or anything described by such information THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PROD UCTS DESCRIBED H...

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