Chapter 3
XV915
25
Advanced Chipset Features
Advanced Chipset Features Menu
The following indicates the options for each item and describes their meaning.
Item
Option Description
DRAM Timing
Manual
DRAM timing is defined by user.
Selectable
By SPD
DRAM timing is defined by SPD.
CAS Latency Time
2,2.5,3
Set CAS latency time.
Auto
DRAM RAS# to
2,3
,4,5
Set DRAM RAS# to CAS# delay 2 SCLKs
CAS# Delay
, 3 SCLKs,4 SCLKs or 5 SCLKs.
Auto
DRAM RAS#Precharge
2,3,4,5
Set DRAM RAS# precharge as 2,3,4 or 5.
Auto
Precharge Delay(tRAS)
4,5,6,7,8,9,10
Set precharge delay time.
Auto
System Memory
Auto
Set memory frequency
Frequency
333MHz
400MHz
533MHz
System BIOS
Enabled
Besides conventional memory, the system
Cacheable
BIOS areais also cacheable.
Disabled
System BIOS area is not cacheable.
