Chapter 3
3 - 7
•
C8000
~
CBFFF
Shadow ...
DC000~DFFFF
Shadow:
Enabled
Disabled
Optional ROM will be copied to RAM by 16K
bytes per unit.
The shadow function is disabled.
•
Delay For HDD
(Secs)
0 ~ 15
Sets the predelay time for hard disk to be ready
for accessing the system.
3.5 Chipset Features Setup
ROM PCI/ISA BIOS (2A59IQ1G)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration
: Enabled
Pipeline Cache Timing
: Faster
DRAM Timing
: 60ns
Chipset NA# Asserted
: Enabled
Mem Drive Str. (MA/RAS)
: Auto
DRAM Leadoff Timing
: 10/6/3
DRAM Refresh Rate
: 15.6us
DRAM Read Burst (EDO/FP)
: x444/x444
DRAM Write Burst Timing
: x222
Fast EDO Leadoff
: Disabled
Refresh RAS# Assertion
: 4 Clks
Fast RAS To CAS Delay
: 3
DRAM Page Idle Timing
: 2 Clks
DRAM Enhanced Paging
: Enabled
Fast MA to RAS# Delay
: 2 Clks
System BIOS Cacheable
: Disabled
Video BIOS Cacheable
: Disabled
8 Bit I/O Recovery Timing
: 1
ESC: Quit
↑↓→←
: Select Item
16 Bit I/O Recovery Timing
: 1
F1 : Help PU/PD/+/- : Modify
Memory Hole At 15M-16M
: Disabled
F5 : Old Values (Shift)F2: Color
PCI 2.1 Compliance
: Enabled
F7 : Load Setup Defaults
Figure 3-4 Chipset Feature Setup
The following indicates the options of each item and describe their
meaning.
Item
Option
Description
•
Auto Configuration
Enabled
Automatically configures DRAM Timing
according to the value of “DRAM Speed
Selection”.
Disabled
Manually configures.
Warning: Do not set DRAM timing too
fast this may affect your system stability.
•
DRAM Timing
60ns,
70ns
This item is of selected DRAM read/write timing. Ensure
your SIMMs are as fast as 60ns, otherwise you have to
select 70ns.
•
RAM Leadoff
These items are regarding DRAM Timing
Summary of Contents for P5I430TX Titanium IB+
Page 1: ...PENTIUM P5I430TX TITANIUM IB...
Page 24: ...Introduction 1 4 This page is intentionally left blank...
Page 32: ...Connector Configuration 2 8...
Page 49: ...Chapter 3 3 17...
Page 50: ......
Page 56: ...P N 430 01011 002...