QDI BrillianX 8V, Manual

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M a nua l f or B r i l l i a nX 8V
Chipset Features Setup
Figure-5 Chipset Features Setup Menu
The following indicates the options for each item and describes their meaning.
Item Option Description
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Bank 0/1, 2/3, 4/5 60ns These items are of selected EDO DRAM
DRAM Timing 70ns read/write timing. You must ensure that your
DIMMs are as fast as 60ns, otherwise you have
to select 70ns.
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SDRAM 3 Define the CLT timing parameter of SDRAM
Cycle Length expressed in 66MHz clocks,
Latency Time = 2 clocks
Latency Time = 3 clocks
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DRAM Read Enabled Enables DRAM Read Pipeline.
Pipeline Disabled Disables DRAM Read Pipeline.
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Cache Rd+CPU wt Enabled Enables Read Around Write.
pipeline Disabled Disables Read Around Write.
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Cache Timing Fast This item is used to select Cache Read/Write
Fastest speed, “Fast” is the optimize selection.
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Video BIOS Enabled Besides conventional memory, video BIOS area
Cacheable is also cacheable.
Disabled Video BIOS area is not cacheable.
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System BIOS Enabled Besides conventional memory, the system BIOS
Cacheable area is also cacheable.
Disabled The system BIOS area is not cacheable.
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Memory Hole At Enabled Memory Hole at 15-16M is reserved for expanded
15Mb Addr PCI card.
Disabled Do not set this memory hole.
Chapter 3