Appendix A Technical Summary
BE-0986 SERIES USER MANUAL
Page: A-24
Configuring WatchDog Timer
The I/O port address of the watchdog timer is 2E (hex) and 2F (hex).
2E (hex) is the address port. 2F (hex) is the data port. User must first
assign the address of register by writing address value into address port
2E (hex), then write/read data to/from the assigned register through
data port 2F (hex).
Configuration Sequence
To program F81966 configuration registers, the following configuration
sequence must be followed:
(1) Enter the extended function mode
To place the chip into the Extended Function Mode, two successive
writes of 0x87 must be applied to Extended Function Enable Registers
(EFERs, i.e. 2Eh or 4Eh).
(2) Configure the configuration registers
The chip selects the Logical Device and activates the desired Logical
Devices through Extended Function Index Register (EFIR) and
Extended Function Data Register (EFDR). The EFIR is located at the
same address as the EFER, and the EFDR is located at address
(EFIR+1). First, write the Logical Device Number (i.e. 0x07) to the
EFIR and then write the number of the desired Logical Device to the
EFDR. If accessing the Chip (Global) Control Registers, this step is not
required. Secondly, write the address of the desired configuration
register within the Logical Device to the EFIR and then write (or read)
the desired configuration register through the EFDR.
(3) Exit the extended function mode
To exit the Extended Function Mode, writing 0xAA to the EFER is
required. Once the chip exits the Extended Function Mode, it is in the
normal running mode and is ready to enter the configuration mode.
