Primare SPA22, Service Manual

Page: 19 / 40

UC_SDA
UC_SCL
RSVDNC1
RX_MUTE
RVSYNC
RSVDNC2
RSDVL
RD1
RD2
RD3
RMCLK
RSCK
RWS
RSD3
RSD2
RSD1
RSD0
RSPDIF
CI2CA_9135
RSVDNC4
EVNODD
RHSYNC
RODCK
RMUTE
TX_D2
TX_D0
TX_D1
RD35
RD29
RD30
RD31
RD15
RD13
RD14
RD28
RD5
RD24
RD16
RD19
RD17
RD18
RD25
RD26
RD27
RD4
RD32
RD33
RD34
TX_D3
RD12
RD22
RD21
RD20
RD6
RD7
RD8
RD10
RD9
RD11
RD23
XO
XI
RSVDNC3
RD0
RST_N
RX_INT
RX_SCDT
RDE
TX_D6
TX_D4
TX_D5
TX_D7
TX_D10
TX_D8
TX_D9
TX_D11
TX_D14
TX_D12
TX_D13
TX_D15
TX_D18
TX_D16
TX_D17
TX_D19
TX_D22
TX_D20
TX_D21
TX_D23
TX_D26
TX_D24
TX_D25
TX_D27
TX_D30
TX_D28
TX_D29
TX_D31
TX_D34
TX_D32
TX_D33
TX_D35
1
2
R7027
4.7K
0603
SMT
1 2
C7108 18PF
0603
1 2
C7109 18PF
0603
R7069 33
1 TP7006
Small
1 TP7003
Small
1
2
R7081
NC
0603
1 TP7005
Small
1 TP7004
Small
R7070 33
1
2
R7026
4.7K
0603
1
TP7002
Small
R7071 33 603
1
2
R7088
1M
0603
R7067 33
R7068 33
GND
VCC3.3
GND
GND
UC_SCL
UC_SDA
MCLK
SCK/DCLK
WS/DR0
SPDIF/DL2
TX_D[35:0]
TPWR_A
RX_INT
RX_SCDT
TXAC+
TXA1-
TXAC-
TXA0-
TXA1+
TXA2+
TXA0+
TXA2-
RST_N
SD0/DL0
SD1/DR1
SD2/DL1
SD3/DR2
RX_MUTE
TX_IDCK
TX_VS
TX_HS
TX_DE
TXA_DSDA
TXA_DSCL
High
State
0x60/0x68 (Default)
Low
0x62/0x6A
RX Config. I2C Addr. Select
Address
SiI9135
AVCC33
38
AVCC33
42
AVCC33
46
AVCC33
50
AVCC33
56
AVCC33
60
AVCC33
64
AVCC33
68
AGND
36
AGND
41
AGND
45
AGND
49
AGND
53
AGND
59
AGND
63
AGND
67
DVCC18
92
DGND2
93
XTALVCC
96
REGVCC
97
CVCC18
143
CVCC18
119
CVCC18
107
CVCC18
91
CVCC18
80
CVCC18
25
CVCC18
12
CGND
142
CGND
130
CGND
118
CGND
106
CGND
90
CGND
79
CGND
23
IOVCC33
6
IOVCC33
32
IOVCC33
74
IOVCC33
88
IOVCC33
104
IOVCC33
113
IOVCC33
137
IOGND
4
IOGND
31
IOGND
73
IOGND
87
IOGND
103
IOGND
112
IOGND
124
IOVCC33
18
IOGND
17
CVCC18
131
CGND
11
EPAD
145
IOVCC33
125
IOGND
136
AGND
71
AVCC18
37
AVCC18
54
AVCC18
72
CVCC18
24
silicon Image
U7014B
SiI9135
REGVCC
RX_AVCC18
GND
GND
GND
GND
DVCC18
XTALVCC
GND
RX_AVCC33 VCC3.3
VCC1.8
PCB LAYOUT: Place all decoupling capacitorsas c lose to the chip as possible
1
2
C7049
0.1uF
0603
1
2
C7054
0.1uF
0603
1
2
C7046
0.1uF
0603
1
2
C7052
0.1uF
0603
1
2
C7055
0.1uF
0603
1
2
C7044
0.1uF
0603
1
2
C7051
0.1uF
0603
1
2
C7047
0.1uF
0603
1
2
C7048
0.1uF
0603
1
2
C7050
0.1uF
0603
1
2
C7045
0.1uF
0603
1
2
C7053
0.1uF
0603
RX_AVCC18
GND GND
VCC3.3
1
2
C7037
0.1uF
0603
FB7006
220ohm@100MHz
0603
1
2
C7043
0.1uF
0603
FB7005
220ohm@100MHz
0603
1
2
C7039
0.1uF
0603
FB7004
220ohm@100MHz
0603
1
2
C7040
0.1uF
0603
1
2
C7038
0.1uF
0603
FB7007
220ohm@100MHz
0603
1
2
C7041
0.1uF
0603
FB7008
220ohm@100MHz
0603
1
2
C7036
0.1uF
0603
1
2
C7042
0.1uF
0603
GND
RX_AVCC33
RX_AVCC33
DVCC18
REGVCC
XTALVCC
RX_AVCC18
VCC3.3
VCC3.3
VCC3.3
VCC1.8
VCC1.8
1
2
C7023
0.1uF
0603
1
2
C7033
0.1uF
0603
1
2
C7026
0.1uF
0603
1
2
C7029
0.1uF
0603
1
2
C7032
0.1uF
0603
1
2
C7030
0.1uF
0603
1
2
C7025
0.1uF
0603
1
2
C7031
0.1uF
0603
1
2
C7034
0.1uF
0603
1
2
C7024
0.1uF
0603
1
2
C7027
0.1uF
0603
1
2
C7035
0.1uF
0603
1
2
C7028
0.1uF
0603
GND
REGVCC DVCC18
GND
XTALVCC
GND GND
VCC1.8
1
2
3
4 5
6
7
8
RP7003
33
1
2
3
4 5
6
7
8
RP7004
33
1
2
3
4 5
6
7
8
RP7001 33
1
2
3
4 5
6
7
8
RP7002 33
1
2
3
4 5
6
7
8
RP7005 33
1
2
3
4 5
6
7
8
RP7006 33
1
2
3
4 5
6
7
8
RP7007 33
1
2
3
4 5
6
7
8
RP7008 33
1
2
3
4 5
6
7
8
RP7009 33
1
2
3
4 5
6
7
8
RP7010 33
1
2
3
4 5
6
7
8
RP7011 33
SiI9135
Q13
140
Q12
141
Q11
144
Q10
1
Q9
2
Q8
3
Q7
7
Q6
8
Q5
9
Q4
10
Q3
13
Q2
14
Q1
15
Q0
16
Q23
126
Q22
127
Q21
128
Q20
129
Q19
132
Q18
133
Q17
134
Q16
135
Q15
138
Q14
139
XTALOUT
94
MUTEOUT
75
MCLK
89
SPDIF
78
EVNODD
22
RSVDL
99
XTALIN
95
R0XC-
39
R0XC+
40
R0X0-
43
R0X0+
44
R0X1-
47
R0X1+
48
R0X2-
51
R0X2+
52
R1XC-
57
R1XC+
58
R1X0-
61
R1X0+
62
R1X1-
65
R1X1+
66
R1X2-
69
R1X2+
70
DSCL0
34
DSDA0
33
INT
102
R0PWR5V
35
R1PWR5V
30
RSVDNC
77
RSVDNC
98
CSCL
27
CSDA
26
DE
19
VSYNC
21
HSYNC
20
ODCK
5
SCDT
101
R
E
SET#
100
DSCL1
29
DSDA1
28
SCK
86
WS
85
SD3
84
SD2
83
SD1
82
SD0
81
Q33
110
Q34
109
Q35
108
Q24
123
Q25
122
Q26
121
Q27
120
Q28
117
Q29
116
Q30
115
Q31
114
Q32
111
CI2CA
105
RSVDNC
55
RSVDNC
76
silicon Image
U7014A
SiI9135
C7114
10UF/16V
C7115
10UF/16V
C7116
10UF/16V
C7117
10UF/16V
C7118
10UF/16V
C7119
10UF/16V
C7120
10UF/16V
1
2
Y7001
28.322MHz
SPDIF/DL2
SD0/DL0
SD1/DR1
SD2/DL1
SD3/DR2
WS/DR0
SCK/DCLK
MCLK
Hansong (Nanjing) Technology Ltd.
Document
Sheet:
Date:
Date:
Date:
Drafted PL R&D Director
by: Checked: Approved:
Number:
THE INFORMATION CONTAINED IN THIS DRAWING IS THE SOLE PROPERTY OF HAN-
SONG TECHNOLOGY CO.,LTD. ANY REPRODUCTION IN PART OF WHOLE WITHOUT
THE WRITTEN PERMISSION OF HANSONG TECHNOLOGY CO.,LTD. IS PROHIBITED
REV. Date ECN No. DESCRIPTION APPRO.
Project: State:
No.HS/QR-RD-25
HS40-SP32_B09 VM1.0-HDMI.SCH
HW Manager
Checked:
VM1.0
Sean
2/6
SP32