Primare CDI10, Service Manual

Page: 6 / 23

A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
ES60x8
硬件版本：
拟制 ： 审核 ：
文件名称：
主机型号 ：
文件编号 ：
日期： 页次：
2005-08
1/7
CDI10
主板原理图
MA[0..11]
DB[0..15]
HD[0..15]
LD[0..12]
VD[0..7]
MA9
DMA3
LA18
MA4
LD7
DMA6
MA4
DB9
LD5
LA8
DB8
LA6
BANK0
MA8
DB12
MA7
MA3
DB2
DMA10
MA7
DMA0
DB1
DB14
MA2
MA5
DQMX
DB4
MA1
LA10
LD6
LA1
DB0
DB7
DB5
MA9
DB14
DB6
LA11
MA10
DMA8
DMA11
LD3
LD1
LA9
DB15
DMA4
DMA2
DMA9
DB7
MA11
DB3
LA12
MA5
MA6
DMA7
LA3
MA10
LA17
DB11
DB10
MA6
DB10
DB15
DB5
DB8
MA11
WE#
DMA1
LA15
BANK1
LA7
LD4
LA0
CKE
DB2
DB3
LA4
CS0#
MA0
MA8
DB13
CAS#
DB11
WRLL#
LCS3#
DB13
LA19
DB12
LA13
MA3
DB1
DB6
DB4
DB9
RAS0#
LA5
LA2
MA2
MA1
LA16
LD0
DB0
DMA5
LD2
LA14
MA0
HRD#
HD3
HWR#
HD0
HA1
HD2
HD7
HD6
HD1
HD4
HD5
HA2
HIRQ
HA0
HD9
HD10
HD11
HD13
HD14
HD15
HIORDY
HIOCS16#
HRST#
HCS3#
HCS1#
HD12
HD8
SDA#
DCLK
SCL#
/H_SYNC
/V_SYNC
27MHz XIN
DCAS#
DCKE
DWE#
DRAS0#
DQM
DMCK
DCS0#
TSD3#
TBCK#
SPDIF#
MCLK#
AUX7
AUX5
CLK_IN
CLK-IN
ESS_RST
LD8
LD9
LD10
LD11
TSD2#
TWS#
TSD1#
TSD0#
LD12
AUX4
AUX6
LA[0..19]
LOE#
HIRQ
HWR#
HRD#
HD[0..15]
HA[0..2]
HRST#
HCS1#
HIORDY
HIOCS16#
HCS3#
LA[0..19]
LCS3#
WRLL#
LOE#
LD[0..12]
VD[0..7]
27MHz
/H_SYNC
/V_SYNC
CLK-IN
27MHz
ESS_SPDIF
IR-IN
CLK-IN
AUX5
AUX6
AUX7
ESS_RST
VCC33
VCC33
VCC25
VCC33
VCC33
VCC33
VCC
VCC33
VCC33
VCC33
VCC VCC
AVCC
EVCC
VCC33
VCC25
AVCC AVCC
RB11 33X4
1 8
2 7
3 6
4 5
U1 ES6028
122
100
123
106
124
9
125
107
126
3
5
127
108
128
1
131
109
132
1
1
1
133
110
134
8
3
135
113
136
1
8
137
114
140
1
2
1
141
115
1
3
9
2
7
1
7
2
4
4
5
9
6
8
7
5
9
2
9
9
5
1
1
0
4
1
3
0
1
4
8
1
5
7
1
5
9
1
6
4
1
8
3
1
9
3
2
0
1
1
2
9
53
2
54
55
3
56
4
57
5
58
6
7
8
10
11
12
13
14
15
16
1
7
19
20
21
22
23
24
2
5
2
6
2
8
2
9
3
0
3
1
32
33
3
4
36
37
38
39
40
41
4
2
4
3
45
46
47
4
8
49
50
5
2
6
0
61
62
63
64
65
66
6
7
69
70
71
72
73
74
7
6
77
78
79
80
81
82
8
4
85
86
87
88
89
90
9
1
93
94
95
96
97
9
8
101
102
1
0
3
105
1
1
2
116
117
118
119
1
2
0
1
3
8
142
143
144
145
146
1
4
7
149
150
151
152
153
154
155
1
5
6
158
160
161
162
1
6
3
165
166
167
168
169
170
1
7
1
173
174
175
176
1
7
7
178
179
180
181
182
1
8
4
185
186
187
188
189
190
191
1
9
2
194
195
196
197
198
199
2
0
0
2
0
2
2
0
3
204
205
206
207
2
0
8
HD0/DCI[0]/EAUX1[0]
DCS0
HD1/DCI[1]/EAUX1[1]
YUV0/CAMYUV2
HD2/DCI[2]/EAUX1[2]
V
C
2
5
HD3/DCI[3]/EAUX1[3]
YUV1/VREF
HD4/DCI[4]/EAUX1[4]
V
C
2
5
HD5/DCI[5]/EAUX1[5]
YUV2/CDAC
HD6/DCI[6]/EAUX1[6]
V
C
3
3
HD7/DCI[7]/EAUX1[7]
YUV3/COMP
HD8/DCI_FDS/EAUX2[0]
A
V
C
C
(V
D
A
C
)
HD9/EAUX2[1]
YUV4/RSET
HD10/EAUX2[2]
V
C
2
5
HD11/EAUX2[3]
YUV5/YDAC
HD12/EAUX2[4]
V
C
3
3
HD13/EAUX2[5]
YUV6/VDAC
HD14/EAUX2[6]
V
C
2
5
HD15/EAUX2[7]
YUV7CAMYUV3
V
C
2
5
V
C
3
3
V
C
2
5
V
C
2
5
V
C
3
3
V
C
3
3
V
C
3
3
V
C
3
3
V
C
3
3
A
V
C
C
(P
L
L
)
V
C
3
3
V
C
3
3
V
C
3
3
V
C
3
3
V
C
3
3
V
C
3
3
V
C
3
3
V
C
3
3
V
C
3
3
V
S
S
DMA0
LA4
DMA1
DMA2
LA5
DMA3
LA6
DMA4
LA7
DMA5
LA8
LA9
V
S
S
LA10
LA11
LA12
LA13
LA14
LA15
LA16
V
S
S
LA17
LA18
LA19
LA20
LA21
RESET
T
D
M
D
X
/R
S
E
L
V
S
S
T
D
M
D
R
T
D
M
C
LK
T
D
M
F
S
T
D
M
T
S
C
TWS/SEL_PLL2
TSD0/SEL_PLL0
V
S
S
TSD1/SEL_PLL1
TSD2
TSD3
MCLK
TBCK
SPDIF/SEL_PLL3
N
C
/C
A
M
V
S
V
S
S
RSD
RWS
RBCK
N
C
/A
P
L
L
XIN
XOUT
A
V
S
S
(
P
L
L
)
V
S
S
DMA6
DMA7
DMA8
DMA9
DMA10
DMA11
V
S
S
DCAS
DSCK/DOE
DWE
DRAS0
DBANK0/DRAS1
DBANK1/DRAS2
V
S
S
DB0
DB1
DB2
DB3
DB4
DB5
V
S
S
DB6
DB7
DB8
DB9
DB10
DB11
V
S
S
DB12
DB13
DB14
DB15
DCS1
V
S
S
DQM
DSCK
V
S
S
CLK
A
V
S
S
(
V
D
A
C
)
PCLK2XSCN/CAMYUV4
PCLKQSCN/CAMYUV5/AUX3[2]
VSSCN/CAMYUV6/EAUX3[1]
HSSCN/CAMYUV7/EAUX3[0]
V
S
S
V
S
S
HWRQ/DCI_REQ/EAUX4[1]
HRDQ/EAUX4[0]
HIRQ/DCI_ERR/EAUX4[7]
HRST/EAUX3[5]
HIORDY/EAUX3[3]
V
S
S
HWR/DCI_CLK/EAUX4[5]
HRD/DCI_ACK/EAUX4[6]
HIOCS16/CAMPCLK/EAUX3[4]
HCS1FX/EAUX3[7]
HCS3FX/EAUX3[6]
HA0/EAUX4[2]
HA1/EAUX4[3]
V
S
S
HA2/EAUX4[4]
AUX0
AUX1
AUX2
V
S
S
AUX3
AUX4
AUX5
AUX6
AUX7
LOE
V
S
S
LCS0
LCS1
LCS2
LCS3
V
S
S
LD0
LD1
LD2
LD3
LD4
V
S
S
LD5
LD6
LD7
LD8
LD9
LD10
LD11
V
S
S
LD12
LD13
LD14
LD15
LWRLL
LWRHL
V
S
S
C
A
M
Y
U
V
0
C
A
M
Y
U
V
1
LA0
LA1
LA2
LA3
V
S
S
R104 OPEN
C112
104
C120
104
RB8 33x4
1 8
2 7
3 6
4 5
R113
4K7 R107
4K7
C132
OPEN
RB13 33x4
1 8
2 7
3 6
4 5
+
C5
100uF
1
2
C122
104
R109
4K7
U5
24C01A
1
2
3
4
5
6
7
8
S0
S1
S2
GND SDA
SCL
WC
VCC
C102
104
R4
1K
C125
104
C124
104
C101
104
R8
FBSMT
R112
OPEN
C103
104
C131
OPEN
R3
1K
C115
104
C127
104
C126
104
Y1 OPEN
R7 33
C109
104
C104
104
RB10 33X4
1 8
2 7
3 6
4 5
C105
104
R108
OPEN
C118
104
C106
104
C12
104
L101 FBSMT
C107
104
R110
OPEN
C108
104
+
C4
100uF
1
2
C110
104
+
C11
100uF
1
2
RB7 33x4
1 8
2 7
3 6
4 5
C113
104
Q1
8050
2
1 3
C123
104
C111
104
+
C10
100uF
1
2
C113
104
C114
104
R114
OPEN
R106
OPEN
C117
104
X1
OSC 27MHz
5
1
8
4
OUT
N/C
VCC
GND
RB12 33x4
1 8
2 7
3 6
4 5
C116
104
U2
4Mx16 SDRAM
1
2
4
6
5
7
3
8
10
12
11
13
9
15
16
17
18
19
35
22
23
24
25
26
14
28
29
30
31
32
33
34
36
37
38
39
40
43
42
44
46
45
47
49
48
50
52
51
53
41
20
21
27
54
VCC
DQ0
DQ1
VSSQ
DQ2
DQ3
VCCQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VCCQ
DQML
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
VSS
A4
A5
A6
A7
A8
A9
NC
CKE
CLK
DQMH
NC
VCCQ
DQ8
DQ9
VSSQ
DQ10
DQ11
VCCQ
DQ12
DQ13
VSSQ
DQ14
DQ15
VSS
BA0
BA1
VCC
VSS
R111
4K7
+
C3
100uF
1
2
C119
104
R105
4K7
RB9 33X4
1 8
2 7
3 6
4 5
C121
104