Prestigio NOBILE 159W, Technical & Service Manual

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and hub interface. The MCH arbitrates between the four interfaces when each initiates an operation.
The Intel
®
855PM memory controller hub (MCH) is designed for use with the Intel
®
Pentium
®
M
processor. The MCH supports data coherency via snooping and must perform address translation for
access to AGP Aperture memory. To increase system performance, the MCH incorporates several
queues.
The Intel
®
855PM MCH may contain design defects or errors known as errata, which may cause
the product to deviate from published specifications. This information will be available in
Specification Updates.
Features
Processor/Host Bus Support
Supports the Intel
®
Pentium
®
M processor
2x Address, 4x Data
Supports system bus at 400 MT/s
Supports host bus Dynamic Bus Inversion (DBI)
Supports 32-bit host bus addressing
12 deep In-Order Queue
AGTL+ bus driver technology with integrated GTL termination resistors and low voltage
operation (1.05 V)
Support for DPWR# signal to Intel
®
Pentium
®
M processor for PSB power
management
Memory System
Directly supports one DDR channel, 64b wide (72b with ECC)
Supports 200-MHz and 266-MHz DDR devices
Supports 64-Mb, 128-Mb, 256-Mb, and 512-Mb technologies for x16 devices and x8 devices.
All supported devices have four banks
Configurable optional ECC operation (single bit Error Correction and multiple bit Error
Detection)
Supports up to 16 simultaneous open pages
Supports page sizes of 2 kB, 4 kB, 8 kB, and 16 kB. Page size is individually selected for every
row.
Thermal throttling scheme to selectively throttle reads and/or writes. Throttling can be
triggered by preset read/write bandwidth limits.
For DDR, Max of two, double-sided SODIMMs (four rows populated) with unbuffered
PC1600/PC2100 DDR (with or without ECC)
By using stacked 512-Mb technology, the largest memory capacity possible is 2.0 GB
TECHNICAL SERVICE MANUAL Prestigio Nobile 159W
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