CRYSTAL
Key
Board
RESET CIR
CUIT
EACH POWER PIN -- A BYPASS CAPACITOR
DSU FROM NAND
UART1 FROM CARD
DSU1 FROM CARD
UART1 FROM NAND
J6 ON DSU MODE
J6 OFF SYSTEM MODE
KEY_STOP : 2.2
V
KEY_DOWN : 0 V
KEY_UP : 0.6 V
KEY_LEFT : 1.5
V
KEY_RIGHT : 2.2
V
KEY_PREV : 0.6
V
KEY_NEXT : 1.5
V
KEY_PAUSE_PLAY : 2.9
4 V
KEY_FUNCTION : 2.94
V
REV 1: 0 V
Stand-By
SCHEMATIC DIAGRAM
MODEL NO .: PF-2821TFT CT955 SCH
NOTE:
subject to change without notice for improvement!
MA6
S
F
_
C
LK
C
V
BS
/WE
MA10
D
S
U
1_
T
X
_1
MA4
MA5
UR
1_
T
X
_1
G
P
C0
MA2
D
A
CG
MA12
D
S
U
1_
R
X
_0
M
S
IN
S#
V
B
US
UR
1_
R
X
_0
MA0
MD2
C
KV
G
P
D4
DC
_
F
BK3
P
C
K1
G
P
D6
UR
1_
R
X
_1
XTALI
DC
P
W
M3
A
O
U
T
_R
MA3
A
M
P
_G
S
T
VU
MD0
P
W
E#
M
B
A0
UR
1_
T
X
_0
UR
1_
R
X
_0
MA1
MD10
/C
AS
S
D
_
D
A
T1
MD7
IO
_
M
U
TE
G
P
C
0
S
M
_
WP
CLK12I
MD5
K
E
Y
_
D
E
T
1X
O
EV
G
P
D5
UR
1_
T
X
_1
DC
_
F
BK1
MA8
/C
S0
MD14
L
RC
S
DC
LK
MD6
D
S
U
1_
T
X
_0
M
D
QM
x
D
_
CD
U
SB
0_
DP
U
SB
0_
DM
A
M
P
_R
N
F
_
C
E4
S
T
VD
G
P
D3
MD12
UR
1_
T
X
_0
S
DC
M
D
/M
SBC
/R
AS
MA9
MD13
CLK12O
A
M
P
_B
D
A
CR
DC
P
W
M1
D
A
CB
O
EH
G
P
D1
UR
1_
R
X
_1
MD9
D
S
U
1_
R
X
_0
MD1
UDC
P
OL
G
P
D2
S
F
_
DO
M
C
LK
/uPRST
A
N
G
E
L_
D
ET
XTALO
A
O
U
T
_L
M
B
A1
S
F
_
S
CN
S
DCD#
MD3
D
S
U
1_
T
X
_0
MA7
/u
P
R
ST
S
T
HL
G
P
D0
MD11
S
F
_
D
IO
MD4
D
S
U
1_
R
X
_1
MD8
MA11
MD15
IR
_
INT
+
3
.3V
K
E
Y
_
D
E
T
0X
S
T
HR
D
S
U
1_
R
X
_1
A
N
G
E
L_
D
ET
K
E
Y
_
D
E
T
1X
S
D
_
D
A
T0
S
D
_
D
A
T3
S
D
_
D
A
T2
K
E
Y
_
D
E
T
0X
IR
_
INT
X
D
_
D0
X
D
_
D1
X
D
_
D2
X
D
_
D3
X
D
_
D4
X
D
_
D5
X
D
_
D6
X
D
_
D7
S
M
_
A
LE
S
M
_
C
LE
S
M
_
R
E#
S
M
_
W
P#
N
F
_
BSY
N
IM
_
I2
C
_
S
CK
N
IM
_
I2
C
_
S
DA
S
M
_
W
E#
K
E
Y
_
D
E
T
0X
K
E
Y
_
D
E
T
1X
N
F
_
C
E
5
D
S
U
1_
T
X
_1
DC
P
W
M2
DC
_
F
BK2
X
D
_
P
W
E#
/C
S0
[2]
S
DC
M
D
/M
SBC
[2]
P
O
L
[4
,5]
M
B
A0
[2]
DC
P
W
M
1
[4]
WP
[2]
M
D
QM
[2]
S
D
_
D
A
T2
[2]
UD
C
[4]
C
V
B
S
[3]
O
E
V
[4]
L
R
C
[4]
A
O
U
T
_
R
[3]
M
C
LK
[2]
/R
AS
[2]
S
F
_
D
IO
[2]
P
C
K
1
[4
,5]
R
T
C
_
R
S
T
[10]
S
T
H
L
[4]
/C
AS
[2]
S
D
_
D
A
T0
[2]
S
F
_
D
O
[2]
U
SB
0_
DM
[2]
S
T
H
R
[4]
P
W
E#
[2]
S
F
_
S
C
N
[2]
DC
_
F
BK
1
[4]
S
T
V
U
[4]
S
T
V
D
[4]
M
B
A1
[2]
V
B
US
[2]
U
SB
0_
DP
[2]
M
D
[0
..
15]
[2]
M
S
IN
S#
[2]
U
SB
_
P
O
W
E
R
_
D
E
T
[2]
S
DC
LK
[2]
O
E
H
[4]
/WE
[2]
S
D
_
D
A
T1
[2]
S
DCD#
[2]
x
D
_
C
D
[2]
C
K
V
[4]
A
O
U
T
_
L
[3]
A
M
P
_
G
[4]
S
D
_
D
A
T3
[2]
S
F
_
C
L
K
[2]
U
SB
_
P
O
W
E
R
1
[2]
M
A
[0
..
12]
[2]
IO
_
M
U
T
E
[3]
DC
_
F
BK
3
[6]
DC
P
W
M
3
[6]
N
F
_
C
E4
[2]
V
O
L_
C
TL
[3]
S
M
_
A
LE
[2]
S
M
_
C
LE
[2]
S
M
_
R
E#
[2]
S
M
_
W
P#
[2]
N
F
_
BSY
[2]
X
D
_
D0
[2]
X
D
_
D1
[2]
X
D
_
D2
[2]
X
D
_
D3
[2]
X
D
_
D4
[2]
X
D
_
D5
[2]
X
D
_
D6
[2]
X
D
_
D7
[2]
N
IM
_
I2
C
_
S
CK
[2]
N
IM
_
I2
C
_
S
DA
[2]
S
M
_
W
E#
[2]
A
M
P
_
R
[4]
A
M
P
_
B
[4]
P
C
K
2
[4
,5]
P
C
K
3
[4
,5]
DC
P
W
M
2
[4]
DC
_
F
BK
2
[4]
X
D
_
P
W
E
#
[2]
V
G
ND
+
3
.3
VV
+
3
.3V
U
SB
_
G
ND
+
3
.3
VC
+1.8V
+
1
.8V
V
G
ND
+
3
.3V
D
G
ND
ADGND
D
G
ND
A
G
ND
D
G
ND
A
G
ND
D
G
ND
A
G
ND
D
G
ND
+
3
.3
VC
+
3
.3
VV
G
ND
A
G
ND
D
G
ND
+
3
.3
VA
S
G
ND
D
G
ND
+
3
.3
VA
A
G
ND
M
G
ND
VA
MP
D
G
ND
V
G
ND
D
G
ND
+
1
.8V
V
G
ND
+
3
.3
VC
+
3
.3V
D
G
ND
D
G
ND
+
1
.8V
+
3
.3
VC
+
3
.3V
U
SB
_
G
ND
+
3
.3
VC
D
G
ND
A
G
ND
S
G
ND
V
G
ND
+
3
.3
VC
+
3
.3V
U
SB
_
G
ND
USB_GND
+
3
.3
VC
D
G
ND
+
5V
D
G
ND
+
3
.3V
+
3
.3
VC
ADGND
N
IM
G
ND
D
G
ND
+
3
.3V
+
3
.3V
D
G
ND
R24
226/1%
R
3
90
SW
1
1
T
A
C
T
SW
12
C2
100n
IR1
IR
R
e
c
e
iv
er
1
2
3
C
237
100n
R
38
10K
SW
13
B
o
w
SW
1
2
J10
P
IN
H
E
A
D
E
R
1
X4
1
2
3
4
L7
FB
80
/1
20
6
R15
8.2K/1%
SW
8
T
A
C
T
SW
12
C5
100n
R
4
4
4
.7K
L6
F
B
600
/0603
R
4
2
4
.7K
R
4
90
C4
100n
R
4
8
4
.7K
C
28
100n
C37
100n
+
E
C
6
47u
/16V
L3
F
B
600
/0805
C7
100n
R
13
3
.3K
R
6
0
1M
C9
100n
SW
2
T
A
C
T
SW
12
SW
9
T
A
C
T
SW
12
R
4
6
4
.7K
C8
100n
J3
P
IN
H
E
A
D
E
R
1
X4
1
2
3
4
C
42
27p
SW
1
0
T
A
C
T
SW
12
C24
100n
C
1
6
100n
L
E
D2
R
ed
2
1
+
E
C4
10u
/16V
C
13
100n
J1
P
IN
H
E
A
D
E
R
1
X4
1
2
3
4
C
40
27p
C
29
10u
/10V
C
15
100n
C
10
100n
R
6
2
10K
+
E
C3
220u
/16V
SW
3
T
A
C
T
SW
12
L
5
F
B
600
/0805
C23
100n
R18
226/1%
C
33
NC
/100n
R
1
1
56
1%
R
5
2
4
.7K
R23
825/1%
CT955
U2
C
T
956
A
_216
2
190
35
36
37
38
39
40
41
42
43
44
45
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
26
24
25
27
28
29
89
32
33
34
46
47
48
49
50
51
68
67
66
65
64
63
62
61
60
58
57
56
55
54
53
52
76
69
70
71
72
73
74
75
77
78
79
80
81
82
83
84
85
86
87
88
59
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
156
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
164
146
147
148
149
150
151
152
153
154
155
157
158
159
160
161
162
163
165
166
167
168
169
170
171
172
173
174
175
177
176
178
179
180
181
182
183
184
185
186
187
188
189
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
1
30
31
GPC[6]/SDCLK/DSU1_TX
V
DD
18
GPC[5]/KEY_DET1/UR2_RX
GPC[4]/D_LATCH1/PWE/UR2_TX
GPC[3]/D_LATCH0
GPC[2]/KS_CLK
GPC[1]/KS_DATA
GPC[0]/KEY_DET0
GPA[0]/SF_CSN/FA[0]/UR1_RX/DSU2_RX
GPA[1]/SF_CLK/FA[1]/UR1_TX/DSU2_TX
GPA[2]/SF_DIO/FA[2]/DSU1_RX/UR2_RX
GPA[3]/SF_DO/FA[3]/DSU1_TX/UR2_TX
VSS
VSSA
VCCA3
TPAD
REFBYPASS
RMIDBYPASS
CVBS_Y
CVBS_C
VSSAX
LPFILTER
VCCAX18
PLL2_VSS3
PLL2_VLF
PLL_VDD3
PLL1_VLF
PLL1_VSS3
VBUS
ID
USB_AVDD3
DN
DP
USB_AVSS3
USB_AVSS18
RREFEXT
USB_AVDD18
VDD18
XTALI
XTALO
AAV
DD3
DFTEN
RESET_N
IR
DCFBK3
DCFBK2
DCFBK1
DCPWM3
DCPWM2
DCPWM1
G
P
D
[6
]/
C
P
H
1
/P
C
LK
G
P
D
[7
]/
C
P
H
2
(R
0
)/S
T
HR
/P
W
M2
G
P
D
[8
]/
C
P
H
3
(R
1
)/S
T
V
U
/DC
P
W
M3
G
P
D
[12
]/
IN
V
(H
M
E)
G
P
D
[13
]/
S
T
HR
G
P
D
[0
]/
S
T
HL
G
P
D
[1
]/
O
E
H
(L
P
)/P
DE
G
P
D
[15
]/
T
C
_
G
P
O1
G
P
D
[5
]/
O
E
V
/T
C
_
G
P
O0
G
P
D
[4
]/
C
L
K
V
/P
VS
G
P
D
[14
]/
S
T
VU
G
P
D
[3
]/
S
T
VD
G
P
D
[2
]/
P
O
L
/P
HS
GPD[9]/PWM1/TC_GPO2
GPD[10]/PWM2
GPD[11]/PWM3
G
PE
[0
]/
S
P
D
IF
G
PE
[7
]/
P
C
M
SD
G
PE
[6
]/
P
C
M
S
D
[0]
G
PE
[5
]/
P
C
M
S
D
[1]
G
PE
[4
]/
P
C
M
S
D
[2]
G
PE
[3
]/
P
C
M
C
LK
G
PE
[2
]/
P
C
M
WS
G
PE
[1
]/
A
C
LK
G
P
A
[31
]/
B
[7
]/
F
D
[7]
G
P
A
[30
]/
B
[6
]/
F
D
[6]
G
P
A
[29
]/
B
[5
]/
F
D
[5]
G
P
A
[28
]/
B
[4
]/
F
D
[4]
G
P
A
[27
]/
B
[3
]/
F
D
[3]
G
P
A
[26
]/
B
[2
]/
F
D
[2]
G
P
A
[25
]/
B
[1
]/
F
D
[1]
G
P
A
[24
]/
B
[0
]/
F
D
[0]
G
P
A
[23
]/
F
W
E
_N
G
P
A
[22
]/
F
O
E
_N
G
P
A
[21
]/
F
A
[21]
G
P
A
[20
]/
F
A
[20]
V
DD3
AAV
SS
A
M
ID
AAV
SS
A
D
A
C
1L
A
D
A
C
2R
AAV
SS
V
R
EF
F
S
A
DJ
V
D
_
AV
SS3
C
V
BS
V
D
_
AV
DD3
R
V
D
_
AV
SS3
G
V
D
_
AV
DD3
B
V
D
_
AV
SS3
H
IV
_
V
SS5
H
IV
_R
HIV_G
HIV_B
HIV_VDD5
GPA[19]/G[7]/FA[19]
GPA[18]/G[6]/FA[18]
GPA[17]/G[5]/FA[17]
GPA[16]/G[4]/FA[16]
GPA[15]/G[3]/FA[15]
GPA[14]/G[2]/FA[14]
GPA[13]/G[1]/FA[13]
GPA[12]/G[0]/FA[12]
GPA[11]/R[7]/FA[11]
GPA[10]/R[6]/FA[10]
GPA[9]/R[5]/FA[9]
GPA[8]/R[4]/FA[8]
GPA[7]/R[3]/FA[7]
GPA[6]/R[2]/FA[6]
GPA[5]/R[1]/FA[5]
GPA[4]/R[0]/FA[4]
VDD18
MD[0]
MD[1]
MD[2]
MD[3]
MD[4]
MD[5]
MD[6]
MD[7]
MDQM
VDD3
MD[15]
MD[14]
MD[13]
MD[12]
MD[11]
MD[10]
MD[9]
MD[8]
M
A
[10]
VSS
MCLK
MA[12]/MCS[1]_N
MA[11]/MCS[0]_N/GPH[0]
MA[9]
MA[8]
MA[7]
MA[6]
MA[5]
MA[4]
MWE_N
MCAS_N
MRAS_N
MCS[0]_N
MBA[0]
MBA[1]/MCS[1]_N/GPH[1]
V
DD3
M
A
[0]
M
A
[1]
M
A
[2]
M
A
[3]
S
V
_
AV
DD3
R
F
IN
LE
FE
TE
R
F
E
NV
FS
F
O
D
AC
S
R
VM
T
RD
AC
S
V
_
AV
SS3
G
P
F
[0
]/
N
F
_
D
[0]
G
P
F
[1
]/
N
F
_
D
[1]
G
P
F
[2
]/
N
F
_
D
[2]
G
P
F
[3
]/
N
F
_
D
[3]
G
P
F
[4
]/
N
F
_
D
[4]
G
P
F
[5
]/
N
F
_
D
[5]
G
P
F
[6
]/
N
F
_
D
[6]
G
P
F
[7
]/
N
F
_
D
[7]
G
P
B
[0
]/
S
L
P
W
M
/N
IM
D
A
TA
G
P
B
[1
]/
S
P
D
P
W
M
/N
IM
P
WM
G
P
B
[2
]/
S
D
E
N
/N
IM
V
LD
G
P
B
[3
]/
S
D
A
TA
G
P
B
[4
]/
S
C
L
K
/N
IM
C
LK
G
P
B
[5
]/
M
IRR
/N
IM
S
YN
G
P
F
[8
]/
N
F
_
A
LE
G
P
F
[9
]/
N
F
_
C
LE
G
P
F
[10
]/
N
F
_
R
EN
G
P
F
[11
]/
N
F
_
W
EN
G
P
F
[12
]/
N
F
_
W
PN
G
P
F
[13
]/
N
F
_
BSY
G
P
F
[14
]/
N
F
_
C
E
[0]
G
P
F
[15
]/
N
F
_
C
E
[1]
G
P
G
[0
]/
N
IM
S
Y
N
/N
F
_
C
E
[2
]/
UR
1_
R
X
/T
R
AY
P
WM
G
P
G
[1
]/
N
IM
V
L
D
/N
F
_
C
E
[3
]/
UR
1_
T
X
/S
M
B
P
WM
G
P
G
[2
]/
N
IM
C
L
K
/N
F
_
C
E
[4
]/
D
S
U
1_
R
X
/UR
2_
RX
G
P
G
[3
]/
N
IM
D
A
T
A
/N
F
_
C
E
[5
]/
D
S
U
1_
T
X
/UR
2_
TX
G
P
G
[4
]/
N
IM
P
W
M
/d
rvv
bus
V
DD3
G
P
C
[15
]/
M
S
IN
S
_N
G
P
C
[14
]/
WP
G
P
C
[13
]/
S
DCD
_N
G
P
C
[12
]/
P
W
E
_N
G
P
C
[11
]/
S
D
_
D
A
T3
G
P
C
[10
]/
S
D
_
D
A
T2
G
P
C
[9
]/
S
D
_
D
A
T1
G
P
C
[8
]/
S
D
_
D
A
T
0
/D
S
U
1_
R
X
/UR
1_
RX
GPC[7]/SDCMD/MSBC/UR1_TX
CLK12XI
CLK12XO
J2
P
IN
H
E
A
D
E
R
1
X4
1
2
3
4
L13
FB600/0805
L9
F
B
600
/0603
C
11
100n
R
4
100
C
1
2
100n
C
39
27p
SW
4
T
A
C
T
SW
12
SW
1
T
A
C
T
SW
12
R
57
10K
+
E
C2
10u
/16V
C
30
100n
C
22
NC
C31
100n
R
4
5
4
.7K
C
27
10u
/10V
C
41
27p
R7
1K
R
4
3
4
.7K
R
4
7
4
.7K
R
1
0
56
1%
C26
33p
+
E
C5
10u
/16V
R
56
4
.7K
C1
100n
J5
P
IN
H
E
A
D
E
R
1
X4
2
1
SW
5
T
A
C
T
SW
12
R22
2K/1%
R
1
2
910
R17
825/1%
L11
FB
80/1206
C
1
7
100n
C6
100n
J6
P
IN
H
E
A
D
E
R
1
X2
1
2
C32
100n
E
C7
NC
/47u
/16V
Q1
B
C
848B
1
2
3
R21
8.2K/1%
R6
1K
L
4
F
B
600
/0805
R
9
56
1%
Y
M2
12M
C3
100n
R55
6.04K
1%
D2
R
L
S
4148
2
1
Y
M1
27M
C236
100n
R
6
1
1M
R
50
R16
2K/1%
C
14
100n
J4
P
IN
H
E
A
D
E
R
1
X3
1
2
3
SW
7
T
A
C
T
SW
12
