11
Signal Descriptions
CS0- (CHIP SELECT 0)
This is the chip select signal from the host used to select the Command Block registers.
CS1 – (CHIP SELECT 1)
This is the chip select signal from the host used to select the Control Block registers.
DA2, DA1, AND DA0 (DEVICE ADDRESS)
This is the 3-bit binary coded address asserted by the host to access a register or data port
in the device.
DASP – (Device active, device 1 present)
This is a time-multiplexed signal which indicates that a device is active, or that Device 1 is
present. This signal shall be an open collector output and each device shall have a 10 k
pull-up resistor.
If the host connects to the DASP- signal for the illumination of an LED or for any other purpose,
the host shall ensure that the signal level seen on the ATA interface for DASP- shall maintain
V
O H
and V
O L
compatibility, given the I
O H
and I
O L
requirements of the DASP-
device drivers.
DD (15:0) (Device data)
This is an 8- or 16-bit bi-directional data interface between the host and the device. The lower 8
bits are used for 8-bit register transfers.
DIOR- (Device I/O read)
This is the read strobe signal from the host. The falling edge of DIOR- enables data from the
device onto the signals, DD (7:0) or DD (15:0). The rising edge of DIOR- latches data
at the host and the host shall not act on the data until it is latched.
DIOW- (Device I/O write)
This is the Write strobe signal from the host. This rising edge of DIOW- latches data from the
signals, DD (7:0) or DD (15:0), into the device. The device shall not act on the data until
it is latched.
DMACK- (DMA acknowledge)
This signal shall be used by the host in response to DMARQ to initiate DMA transfers.
DMARQ (DMA request)
This signal, used for DMA data transfer between host and device, shall be asserted by the
device when it is ready to transfer data to or from the host. The direction of data transfer is
controlled by DIOR- and DIOW-. This signal is used in a handshake manner with DMACK- i.e.,
the device shall wait until the host asserts DMACK- before negating DMARQ, and
re-asserting DMARQ if there is more data to transfer.
This line shall be released (high impedance state) whenever the device is not selected or is
selected and no DMA command is in progress. When enabled by DMA transfer, it shall be
driven high and low by the device.
When a DMA operation is enabled, CS0- and CS1- shall not be asserted and transfers
shall be 16-bits wide.
