Introduction
ROBO-598 User’s Manual
1-8
Page 1: ...hipset integrates floppy controller two serial ports one FIR Fast Infra Red port and one parallel port Two high performance 16C550 compatible UARTs provide 16 byte FIFOs and the multi mode parallel port supports ECP EPP SPP function Besides two USB Universal Serial Bus ports provide high speed data communication between peripherals and PC The PICMG standard makes the ROBO 598 works with the legacy...
Page 2: ...er One Printer cable One FDC cable One IDE cable One 5 pin to 5 pin keyboard cable for Backplane connection One 4 pin ATX power control cable for Backplane connection One CD title to support PCI IDE AGP display and Graphics drivers If any of these items is damaged or missed please contact your vendor and save all packing materials for future replacement and maintenance ...
Page 3: ...rst Static RAM Chipset ALi M1541 M1543C Aladdin 5 Bus Interface Follow PICMG standard 32 bit PCI and 16 bit ISA Fully complies with PCI bus specification V2 1 AGP specification V1 0 compliant PCI IDE Interface Supports two enhanced IDE ports up to four HDD devices with PIO mode 5 and Ultra DMA 33 mode 2 timing feature Floppy Drive Interface Supports one FDD port up to two floppy drives and 5 1 4 3...
Page 4: ...endar RTC Real Time Clock calendar with battery backup for 10 year data retention Watchdog Timer 0 5 1 2 4 8 16 32 64 sec time out intervals by jumper setting Disk On Chip DOC Feature Reserved one 32 pin socket for M system Flash Disk up to 72MB On board VGA Feature 3D ATI RAGE PRO AGP display with 4MB 8MB SGRAM and one DSUB 15 VGA connector to support max resolution of 1600x1200 at 65K colors CPU...
Page 5: ...ntal Requirements Outline Dimension L X W 339 5mm 13 36 X 121 5mm 4 78 Board Weight 0 9 lb 0 41kg PCB layout 6 layer Power Requirements 5V 10 0A typ 12V 80mA 12V 20mA Operating Temperature 0 60 32 140 Storage Temperature 20 80 Relative Humidity 5 95 non condensing ...
Page 6: ... coherence for optimizing CPU bus utilization The on board L2 cache is configured for Pipelined Burst SRAM with cache size 512KB in factory default The cacheable region can be up to 128MB cache memory configuration by using 8 bit TAG RAM or using internal TAG SRAM to acquire cacheable region up to 512MB The South Bridge M1543C provides a highly integrated PCI to ISA bridge solution for the best in...
Page 7: ...OARD MOUSE AGP BUS ISA BUS PCI BUS 12 CPU DRAM DRAM SRAM M1541 M1531 M1543 Figure 1 1 ROBO 598 System Block Diagram PENTIUM CPU M1541 456 BGA SRAM TAG DRAM 3 DIMM M1543C 328 BGA IDE 1 IDE 2 USB connectors 2UART LPT FDD FIR BIOS RTC BUFFER WDT DOC CLOCK GENERATOR ATI 3D RAGE PRO VGA 256 BGA WITH SGRAM 4M 8MB CLOCK BUFFER ...
Page 8: ...Introduction ROBO 598 User s Manual 1 8 ...
