PLX Technology PEX 8648 White Paper Download Page 13

Using PEX 8648 SMA Based (SI) Card White Paper – Version 1.3 
© 2010 by PLX Technology, Inc. All Rights Reserved 

 

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9  Using Packet Generator in Two Card Set 

In this example, the PLX PEX 8648 Packet Generator and Monitor features are used to generate PCI 
Express heavy traffic across the link under test. 

  Step 1) Program Port 3 as upstream port on card # 2 as outlined in Loopback test. 

  Step 2) Install cards as outlined in Loopback test. 

  Step 3) Programming packet generator and monitor features 

o

  Under programs bring up “PLX GENMON” 

o

  Go to ‘Performance Monitor’ box at top of screen. SI cards are identified by bus number. 

The device nearest the root complex will have the lower bus number. Select this device 
as monitor (either will work). Now depress “Open Monitor” button.  

o

  With Monitor screen now open, select “Port 3 Ingress” and “Port 3 Egress”. You can 

optionally deselect the Port 0 monitors. Depress “Start”. Minimize screen. 

o

  Starting Traffic Generator:  

ƒ

  Go back to main GENMON screen. Select the PEX 8648 chip with the higher bus 

number – this is the required traffic generator. Go to “Load File” and load the SI 
Card supplied script “Upstream_Exerciser.PLE”. Depress “Start”. 

o

  Looking at the Monitor screen – traffic should now be evident. 

  Step 4) Check bad DLLP and bad TLP counters in 8648 on card #1 and card #2 

o

  Start standard SDK software. 

o

  In either chip read Port 3 memory mapped registers for TLP/DLP error count. (Registers 

x31E8h / x31ECh) These registers keep a running tab of DLLP and TLP errors on Port 3. 
To clear write all “0” to each register. 

  Step 5) Change SerDes settings and check for errors. 

Summary of Contents for PEX 8648

Page 1: ...EX 8648 SMA based SI Card White Paper Version 1 3 July 2010 Website www plxtech com Technical Support www plxtech com support Copyright 2008 by PLX Technology Inc All Rights Reserved Version 1 3 July...

Page 2: ...ut adjust transmitter and receiver settings check Gen 1 Gen 2 link up thru a channel operate at a max x4 width check system errors run loopback and card to card signal integrity SI testing Figure 1 PL...

Page 3: ...ception without the degradation of the PCIe connector The transmitter and receiver pairs of each lane of the port are clearly marked with lane and polarity however it is not necessary to track lane po...

Page 4: ...urce of degraded signal performance If a clock other than the PCIe connector system clock is desired the PCB can be modified to accept an external differential clock via SMA J17 18 and relocation of z...

Page 5: ...ister manipulation without an I2 C controller To move from signal observation to an adjustable PCIe link bin files are supplied which demonstrate how to convert the SMA port to the upstream link and o...

Page 6: ...register 0234h Return bits 19 16 to 0 Terminated link is now in Gen 2 Compliance mode If it is desired to change the TX swing and emphasis settings it can be done as below without resetting the chip...

Page 7: ...8 Data Book Table 19 11 setting of 19h o Receiver equalization left at default 0 o Signal Detection Threshold EIDLE set to minimum 0 for Port 3 only For RX equalization Port 3 SMA outputs is controlle...

Page 8: ...Tools Select Find I2C Device 3 Locate and click I2C Scan button Type 68 for device address Next locate Select I2C Device Type and pull down 8648AB Next depress Find Devices You should see 8648AB appea...

Page 9: ...er card or second device nearer the root complex by SMA coax cables note cables are equal length Connect TX to RX and RX to TX of the two devices Match lane numbers For x1 use Lane 0 For x2 use Lane 0...

Page 10: ...both cards to see at least one reset in order to initiate link up negotiation If needed manually depress card reset switch 2 Two root complex systems each SI card is placed in a PC and the SMA ports...

Page 11: ...d 1 to RX of card 2 Match Lane numbers For x1 use Lane 0 for x2 use Lane 0 and Lane 1 You can add backplane in the path once you have verified that the initial setup works Digital Loopback Test o Rebo...

Page 12: ...Register 210h through 21Ch with desired data pattern o Enable Loopback Master Set Physical Layer Port Command Register 230h 12 Verify bit 15 is set o Enable User Test Pattern Set Physical Layer Test R...

Page 13: ...s device as monitor either will work Now depress Open Monitor button o With Monitor screen now open select Port 3 Ingress and Port 3 Egress You can optionally deselect the Port 0 monitors Depress Star...

Page 14: ...requires several writes to the base register in Station 0 Port 0 and a write to the Port 3 specific register As a point of clarity note that Port 3 consists of SerDes numbers 12 15 Port 3 Lane 0 3 Th...

Page 15: ...low Figure 8 Example of Programming for Slave Loopback via EEPROM Note the above bin file is provided as part of the SI card documentation Using the PEX SDK this bin can be directly programmed into th...

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