— 6 —
SCPH-9000
SERIES
Reproduction Prohibited
RES3.3
127
128
126
125
124
122
123
131
134
DQM1
DQM3
DQM0
DQM2
WE
CAS
RAS
CS
DSF
CLK
56
57
23
24
25
26
27
28
53
55
DQMH
DQML
WE
CAS
RAS
MCS0
DSF
MCLKOUT
MCLKIN
MUTO
AOUTL
AOUTR
154
147
150
105
6
24-28, 31-36, 39-42,
45-50, 53-59, 62-65
SR0-SR7
77-79, 82-86
89-95, 98-104
107-112, 115-118
RST
137-140
143-145
148-150
29, 31-34
47-51
1, 3, 4, 6, 7, 9, 10,
12, 13, 17, 18, 20,
21, 60, 61, 63, 64,
68, 69, 71, 72, 74,
75, 77, 78, 80, 81,
83, 84
D0-D31
GPU
FD0-FD31
LA0-LA9
DQ0-DQ31
A0-A9
IC203
VIDEO DAC + RGB ENCODER
IC502
IC201
SG RAM
SD0-SD15
1, 2, 5-14
16-19
20-27, 30
R
DECODER
R
SG0-SG7
G
DECODER
G
SB0-SB7
C SYNC
NTPL
SPMUTE
AU-R
AU-L
SPMUTE
RESET
B
DECODER
CELL
MATRIX
CELL
MATRIX
CELL
MATRIX
BURST
FLAG
Y/C
M/X
CHROMA
GEN.
SYNC
ADD
LATCH
LATCH
LATCH
SCF
APC
SCF
CLOCK DIVIDER
CLAMP
CLAMP
MATRIX
CLAMP
B
HD0-HD15
HA1-HA8
IC732
SD0-SD15
125-142
105,107-111,113-116
85-92
97-99,101,102
HD0-HD15
DTIB
BCK0
LRC0
CD-ROM CONT CD DSP
4Mbit DRAM
IC310
CD-RF
PDIC
KSM440AEM
IC723
14
15
13
SYNC IN
SC IN
NT/PAL
B-Y
R-Y
Y
B
G
R
156
157
181
179
182
178
OE
WE
RAS
UCAS
LCAS
27
57
55
53
54
58
59
11
12
13
14
17
18
15
16
122
SPEED
RESET
6
7
5
4
22
23
2
3
20
37
38
39
RFAC
TFDR
TRDR
FRDR
FFDR
SRDR
SFDR
SRD
SWR0
SYSCLK1
FE
SE
XOE
XWE
XRAS
XCAS
119
120
144
XHRD
XHWR
SYSCK
27
13
14
28
29
LPF
BPF
Y TRAP
6dB
75
75
75
6dB
75
6dB
75
6dB
75
MD0-MD15
2-5, 7-10
31-34, 36-39
16-19, 22-26
160-164, 166-172
174-177
MA1-MA9
MED0-MED15
MEA0-MEA8
183-186, 188-192
I/O 1-16
7
6
PD1
PD2
5
4
E
F
MI
LD
TRK–
TRK+
FCS–
FCS+
SL–
SL+
SP–
SP+
SLED
MOTOR
FOCUS
COIL
TRACKING
COIL
8
A0-A8
HA0-HA9
SA0-SA9
SUB CPU
I/F
CLV
PROTECTOR
LEVEL
SHIFT
IC722
DRIVER
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
SWITCH
AND
BUFFER
MIRR
DFCT
FOK
SERVO DSP
TRACKING
PWM
GENERATOR
TRACKING
PWM
GENERATOR
TRACKING
PWM
GENERATOR
TIMING
GENERATOR
PWM
GENERATOR
A/D
CONVERTER
SYNC
PROTECTOR
5
6
7
SPCLK
19
18
12
13
2
VREFL
VOOM
M_R
TRM_L
TRM_R
+5V
IC405
7
4
5
11
REG
Q701
SERIAL INPUT
INTERFACE
8x
INTERPOLATOR
XLT1
8x
INTERPOLATOR
∆∑
MODULATOR
∆∑
MODULATOR
502-2
LD
702-12
M_G
502-1
M_B
502-4
M_Y
502-8
M_C
502-6
M_VIDEO
502-7
M_AUL
502-11
M_AUR
+B
9
502-9
702-7
702-6
702-8
702-4
702-9
702-1
702-10
702-15
702-14
702-16
702-13
701-1
701-2
701-4
701-3
AMP
AMP
AMP
AMP
AMP
AMP
AMP
BUFF
BUFF
BUFF
BUFF
BUFF
BUFF
BUFF
BUFF
AMP
AMP
AMP
SPINDLE
MOTOR
BLOCK
M
LASER DIODE
13
2
14
199
17
12
9
5
4
3
1
206
192
15
13
11
12
16
IREQ
A2
H BLANK
PCK
V BLANK
DREQ
SYSCLK
DACK
WR
RD
CS
D SYSCK
VCKN-A
GPUNIT
GPUA2
H BLANK
PCK
V BLANK
GPUDREQ
SYSCLK0
GPUDACK
GPUWR
GPURD
GPUCS
DBLCLK
RES3.3
36
35
34
32
33
31
41
96
DREQ
XIRQ
DACK
XRD
XWR
XCS
SYSCLK1
DTIB
SPUDREQ
SPUNIT
SPUDACK
SRD
SWR0
SPUCS
SYSCLK1
EXTDATA
74
75
76
77
80
81
11
94
95
96
79
82
103
117
DATA
XLAT
CLOK
SCOR
SQCK
SQS0
FSOF
XCS
XWR
XRD
XINT
SENS
XHCS
H INT
SPUDREQ
SRD
SWR0
SPUDACK
SYSCLK1
SA1-SA9
AV MULTI OUT
24
22
23, 25-31
1-12
13-15,
17-21
OE
CE
BOOT RAM
IC102
SRD
44
27
2-5, 7-10,13-16,18-21
50-53,55-58,61-64,66-69
28-34, 37-39
WE
RAS
I/O1-I/O32
A0-A9
33-38, 40, 41
6-10
SUB CPU
IC304
S301
DECD0-DECD7
19
DECA0-DECA4
DOOR
SPEED
DAT0
XLT0
CLK0
SCOR
SQCK
SUB Q
LS
MCLK
XRST
MCS
MWR
MRD
MINT
SENS
CD RD CS
CD RD INT
27
43
44
45
31
26
24
18
14
13
46
47
48
30
23
SPEED
DATA
XLT
CLK
SCOR
SQCK
SUB Q
LMTSW
DSC1
RESET
DECCS
DECWR
DECRD
X INT
SENSE
LDON
AGC_CNT
49
28
LDON
MIRROR
OE
45-48
HYPER DRAM (16M)
IC106
IC106
CAS1-4
A0-A19
D0-D7
MCA0-MCA4
MCA0-MCA4
MCD0-MCD7
MCD0-MCD7
FROM IC103
DMA
TIMING
GEN
HOST
IF
ENV
SERIAL
IF
DSP
8x
INTERPOLATOR
8x
INTERPOLATOR
SERIAL
INPUT
INTERFACE
EXRAM
IF
∆∑
MOD
SCF
∆∑
MOD
SCF
FROM IC103
81
83
84
80
77
82
89
SCK0
TXD
RXD
DTR0A
DTR0B
DSR
INT
102-10
102-8
102-6
102-5
102-3
102-2
102-1
75
73
74
71
72
70
VD0-VD31
SD0-SD15
SA0-SA23
CS2
RXD
DSR
TXD
CTS
DTR
RTS
5 67MHz
6
3.58MHz (NTSC)
4.43MHz (PAL)
1
53.63MHz (NTSC)
53.20MHz (PAL)
SCK0
TXD0
RXD0
DTR0A
DTR0B
DSR0
INTIN10
SIO
161-165, 172-181, 184-194, 197, 198
MAIN DATA BUS (GPUD0-GPUD31)
RXD1
DSR1
TXD
CTS1
DTR1
RTS1
97
4
3, 4
CRYSTALP
Q106 (1/2)
Q106 (1/2)
Q105 (1/2)
Q105 (1/2)
104-1
104-3
104-4
104-5
104-6
104-8
CONTROLLER
SERIAL I/O
CPU
IC103
EP ROM
CONFIGURABLE
MULTIPLEXER
AND
DIVIDE LOGIC
DWE
DRAS0
DCAS0-DCAS3
43
45
46-49
DD0-DD31
5-13, 16-25,
28-37, 40-42
DA0-DA7
DA9
DA11
55, 57, 59-64
67, 68
107-116, 119-142
145-152, 132-142, 125-129
PLL 1
IC204
X201
14.318182MHz (NTSC)
17.37MHz (PAL)
REF.
OSC
PLL 2
PLL 3
4
SYSTEM
RESET
DC-AC
CONV.
SWITCHING
REG.
ADDRESS BUS (SA0-SA23)
SUB DATA BUS (SD0-SD15)
SRD
SWR0
SYSCLK1
101
100
154
RES3.3
SRD
SWR0
SYSCLK1
95
94
CS5
INT IN2
88
90
87
96
SPUDREQ
SPUNIT
SPUDACK
SPUCS
DREQ4
INT IN9
DACK4
CS4
102
153
159
160
199
200
201
202
203
204
205
206
GPUNIT
GPUA2
H BLANK
PCK
V BLANK
GPUDREQ
SYSCLK0
GPUDACK
GPUWR
GPURD
GPUCS
DBLCLK
INT IN1
VA2
TCLK1
TCCK0
INT IN0
DREQ2
SYSCLK0
DACK2
VWR
VRD
CS7
DSYSCLK
+5V
REG.
+8V
+3.5V
REG.
+5V
SER +3.5V
RECT.
RECT.
FULL
WAVE
RECT.
UC
AUS/UK/AEP
POWER SUPPLY BLOCK
PU-23 BOARD
2A/125V
1.6A/250V
F001
RECT.
+8V
+3.5V
MDEC
CPU CORE
B/U
DRAM
CONTROLLER
GTE
