EL640.480-A SB Series Operations Manual (020-0358-00A)
6
Power and Control Inputs
Table 2. Power and Control Inputs
Pin Signal
Symbol
Description
J2 (Power input connector)
1
Voltage
Vcc2
Supply voltage (+12 Vdc) converted to required internal
voltages
2 Ground
GND
Power
return
3
Ground
GND
Power return (same as pin 2)
4
Reserved
Reserved for compatibility with Vcc1 input in other Planar
displays. Do not use.
J3 (Luminance control input)
1 Luminance
control
LUMPOT1
The inputs for an external 50 k
Ω
log potentiometer to
adjust the luminance of the display. If left disconnected,
the luminance is at the max level. See page 9 for details.
2 Luminance
control
LUMPOT2
Control Basics
The EL panel is a matrix structure, with column and row electrodes arranged in
X-Y formation. Light is emitted when an AC voltage of sufficient amplitude is
applied at a row-column intersection. The display operation is based on the
symmetric, line at a time data addressing scheme. Input thresholds to the
display are 74ACT CMOS compatible (TTL thresholds).
Power Input
The only required supply voltage for the display is +12Vdc (Vcc2). All internal
high voltages are generated from Vcc2.
Connectors
Table 3. Connectors.
J1
34-pin header
ODU 511.266.003.034 or eq.
Mating
ODU
517.065.003.034
or
eq.
Locking clip
ODU 511.065.734.700 or eq.
J2
4-pin header
Hirose DF1–4P–2.5 DS or eq.
Mating
Hirose
DF1–4S–2.5
R
24
Protector Hirose
DF1–4A
1.33
J3
2-pin header
Hirose DF1–2P–2.5 DS or eq.
Mating
Hirose
DF1–2S–2.5
R
24
Protector Hirose
DF1–2A
1.33
