XV-DV350
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TAS5508APAG (W51 DAMP ASSY : IC3101)
• 8 ch Digital Audio PWM Processor
Pin Arrangement (Top view)
1
VRA_PLL
2
PLL_FLT_RET
3
PLL_FLTM
4
PLL_FLTP
5
AVSS
6
AVSS
7
VRD_PLL
8
AVSS_PLL
9
AVDD_PLL
10
VBGAP
11
RESET
12
HP_SEL
13
PDN
14
MUTE
15
DVDD
16
DVSS
VR_PWM
48
PWM_P_4
47
PWM_M_4
46
PWM_P_3
45
PWM_M_3
44
PWM_P_2
43
PWM_M_2
42
PWM_P_1
41
PWM_M_1
40
VALID
39
DVSS
38
BKND_ERR
37
DVDD
36
DVSS
35
DVSS
34
VR_DIG
33
17
VR_DPLL
18
OSC_CAP
19
XTL_OUT
20
XTL_IN
21
RESERVED
22
RESERVED
23
RESERVED
24
SDA
25
SCL
26
LRCLK
27
SCLK
28
SDIN4
29
SDIN3
30
SDIN2
31
SDIN1
32
PSVC
RESERVED
64
MCLK
63
PWM_HPPR
62
PWM_HPMR
61
PWM_HPPL
60
PWM_HPML
59
PWM_P_6
58
PWM_M_6
57
PWM_P_5
56
PWM_M_5
55
DVDD_PWM
54
DVSS_PWM
53
PWM_P_8
52
PWM_M_8
51
PWM_P_7
50
PWM_M_7
49
Pin Functions
No.
Pin Name
I/O
Pin Function
1
VRA_PLL
−
Voltage reference for PLL analog supply 1.8 V.
2
PLL_FLT_RET
O
PLL external filter return
3
PLL_FLTM
O
PLL negative input. Connected to PLL_FLT_RTN via an RC network
4
PLL_FLTP
I
PLL positive input. Connected to PLL_FLT_RTN via an RC network
5
AVSS
−
Analog ground
6
AVSS
−
Analog ground
7
VRD_PLL
−
Voltage reference for PLL digital supply 1.8 V.
8
AVSS_PLL
−
Analog ground for PLL.
3.3-V analog power supply for PLL
System reset input, active low.
Soft mute of outputs, active low (Muted signal = a logic low, normal operation = a logic high)
Digital power 3.3-V supply for digital core and most of I/O buffers
Digital ground for digital core and most of I/O buffers
Voltage reference for digital PLL supply 1.8 V.
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device.
20
XTL_IN
I
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device.
21
RESERVED
−
Connect to digital ground
22
RESERVED
−
Connect to digital ground
23
RESERVED
−
Connect to digital ground
24
SDA
I/O
I2C serial control data interface input / output
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299