DVH-P5900MP/XN/EW5
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8.3 SYSTEM MICROCOMPUTER TEST PROGRAM
-
PCL Output
In the normal operation mode (with the detachable panel installed, the ACC switched ON, the standby mode
cancelled), shift the TESTIN IC601(Pin 86) terminal to H.
The clock signal is output from the PCL terminal IC601(Pin 37).
The frequency of the clock signal is 468.750 kHz that is one 32th of the fundamental frequency.
The clock signal should be 468.750 kHz(
±
19 Hz).
If the clock signal is out of the range, the X'tal (X601) should be replaced with new one.
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