DV-47Ai
138
1
2
3
4
1
2
3
4
C
D
F
A
B
E
Pin Name
Pin No
I/O
Description
HSDI1_AMCLK_IN
169
I
Audio Master Clock Input. This clock is used to decode the bi-
phase encoding of 60958 data.
This pin is also used to input the 1.5*BCK for Flow Control
mode.
MLPCM Interface, HSDI1 Audio Port, and HSDI1 video port
share buffer 1. Only one interface can access the buffer at a
time.
HSDI1_AMCLK_OUT
170
O
Audio Master Clock Output. This clock is derived from the
VCO_CLK input. 60958 data output from iceLynx-Micro is bi-
phase encoded using this clock.
HSDI1_AUDIO_ERR
171
O
Audio Error Signal. iceLynx-Micro asserts this signal
whenever an Audio Error condition occurs. (Receive from
1394 only.)
HSDI1_AUDIO_MUTE
172
O
Audio Mute Status. iceLynx-Micro asserts this signal
whenever an Audio Mute condition has occurred, and
hardware has muted the HSDI1 audio interface. (Receive
from 1394 only.)
HSDI1_AV
155
O
HSDI Port 1 Available. Programmable. Default active low.
For receive from 1394, this signal indicates if a 1394 packet is
available in the receive buffer for reading. The HSDI_AV
signal for MPEG2 data also depends on time stamp based
release.
For transmit onto 1394, this signal can be used to indicate
buffer level in HSDI TX mode 8 and 9 by programming a CFR.
This pin can be used to indicate buffer level in transmit mode
by programming a CFR. If the buffer level is above a
programmed level, HSDI_AV is asserted.
HSDI1_CLK
153
I/O
HSDI Port 1 Clock. Programmable. Default rising edge
sample. This clock is used to operate the HSDI port 1 logic.
In parallel mode, the maximum clock is 27MHz. In serial
mode, the maximum clock is 70MHz.
This signal can be used as HSDI1_SACD_MCLK for SACD
Transmit and Receive.
MLPCM Interface, HSDI1 Audio Port, and HSDI1 video port
share buffer 1. Only one interface can access the buffer at a
time.
HSDI1_D0
158
I/O
HSDI Port 1 Data 0 Pin. Data 0 is the least significant bit on
the HSDI data bus. In serial mode, only HSDI0_D0 is used.
This signal can be used as HSDI1_SACD_D0 for SACD
Transmit and Receive.
Summary of Contents for DV-47Ai
Page 19: ...DV 47Ai 19 5 6 7 8 5 6 7 8 C D F A B E ...
Page 36: ...DV 47Ai 36 1 2 3 4 1 2 3 4 C D F A B E 3 10 FLKY and KEYB ASSYS E FLKY ASSY VWG2357 E ...
Page 38: ...DV 47Ai 38 1 2 3 4 1 2 3 4 C D F A B E 3 11 ILKB ASSY I ILKB ASSY VWG2391 I D D D D D D D D D ...
Page 122: ...DV 47Ai 122 1 2 3 4 1 2 3 4 C D F A B E Pin Function ...
Page 123: ...DV 47Ai 123 5 6 7 8 5 6 7 8 C D F A B E ...
Page 143: ...DV 47Ai 143 5 6 7 8 5 6 7 8 C D F A B E 7 3 DISC CONTENT FORMAT PLAYBACK COMPATIBILITY ...
Page 145: ...DV 47Ai 145 5 6 7 8 5 6 7 8 C D F A B E 8 PANEL FACILITIES ...
Page 146: ...DV 47Ai 146 1 2 3 4 1 2 3 4 C D F A B E ...
Page 147: ...DV 47Ai 147 5 6 7 8 5 6 7 8 C D F A B E ...