DV-2850-S
72
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4
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C
D
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B
E
No.
Pin Name
I/O
Pin Function
No.
Pin Name
I/O
Pin Function
220 ASDATA3
I/O
Audio serial data 3 (Center-back/Center-left-
back/Center-right-back, in 6.1 or 7.1 mode)
DSD data right surround channel
Trap value in power-on reset:
1:manufactory test mode
0:normal operation
While only 2 channels output:
GPIO
221 DVDD18
–
1.8V power pin for internal digital circuitry
222 ASDATA4
I/O
Audio serial data 4 (Down-mixed Left/Right)
DSD data center channel
Trap value in power-on reset:
1:manufactory test mode
0:normal operation
While only 2 channels output:
Microcontroller external interrupt 1
GPIO
223 DVSS
–
3.3V Ground pin for internal digital circuitry
224 MC_DATA
I/O
Microphone serial input
While not support Microphone:
Microcontroller external interrupt 2
GPIO
225 SPDIF
O
SPDIF output
226 RFGND18
–
Analog ground
227 RFVDD18
–
Analog power 1.8V
228 XTALO
O
27M crystal out
229 XTALI
I
27M crystal in
189 DACVDDC
–
3.3V power pin for VIDEO DAC circuitry
230 JITFO
O
The output terminal of RF jitter meter
190 VREF
–
Bandgap reference voltage
231 JITFN
I
The input terminal of RF jitter meter
191 FS
–
Full scale adjustment
232 PLLVSS
–
Ground pin for data PLL and related analog circuitry
192 YUV0
O
Video data output bit 0
Compensation capacitor
233 IDACEXLP
O
Data PLL DAC Low-pass filter
193 DACVSSC
–
Ground pin for VIDEO DAC circuitry
234 PLLVDD3
–
Power pin for data PLL and related analog circuitry
194 YUV1
O
Video data output bit 1
Analog Y output
235 LPFON
O
The negative output of loop filter amplifier
195 DACVDDB
–
3.3V power pin for VIDEO DAC circuitry
236 LPFIP
I
The positive input terminal of loop filter amplifier
196 YUV2
O
Video data output bit 2
Analog chroma output
237 LPFIN
I
The negative input terminal of loop filter amplifier
197 DACVSSB
–
Ground pin for VIDEO DAC circuitry
238 LPFOP
O
The positive output of loop filter amplifier
198 YUV3
O
Video data output bit 3
Analog composite output
199 DACVDDA
–
3.3V power pin for VIDEO DAC circuitry
200 YUV4
O
Video data output bit 4
Green or Y
201 DACVSSA
–
Ground pin for VIDEO DAC circuitry
202 YUV5
O
Video data output bit 5
Blue or CB
203 YUV6
O
Video data output bit 6
Red or CR
204 DVDD3
–
3.3V power pin Video DAC digital circuitry only
205 VSYN
I/O
Vertical sync input/output
While no External TV-encoder:
Vertical sync for video-input
Version AD input port 1
GPIO
206 YUV7
I/O
Video data output bit 7
While no External TV-encoder:
Microcontroller external interrupt 3
Audio serial data 5 part II:DSD data sub-
woofer channel or Microphone output
GPIO
207 HSYN
I/O
Horizontal sync input/output
While no External TV-encoder:
Horizontal sync for video-input
Microcontroller external interrupt 4
Version AD input port 2
GPIO
208 SPMCLK
I/O
Audio DAC master clock of SPDIF input
While SPDIF input is not used:
Serial interface port 0 clock pin
GPIO
209 SPDATA
I/O
Audio data of SPDIF input
While SPDIF input is not used:
Serial interface port 0 data-in
GPIO
210 SPLRCK
I/O
Audio left/right channel clock of SPDIF input
While SPDIF input is not used:
Serial interface port 0 data-out
GPIO
211 SPBCK
I/O
Audio bit clock of SPDIF input
While SPDIF input is not used:
Serial interface port 0 chip select
Audio serial data 5 part I:DSD data sub-
woofer channel or Microphone output
GPIO
212 DVDD3
–
3.3V power pin for internal digital circuitry
219 ASDATA2
I/O
Audio serial data 2 (Center/LFE)
DSD data left surround channel
Trap value in power-on reset:
1:manufactory test mode
0:normal operation
While only 2 channels output:
GPO
213 ALRCK
I/O
Audio left/right channel clock
Trap value in power-on reset:
1:use external 373
0:use internal 373
214 ABCK
O
Audio bit clock
Phase de-modulation
215 ACLK
I/O
Audio DAC master clock
216 DVSS
–
1.8V Ground pin for internal digital circuitry
217 ASDATA0
I/O
Audio serial data 0 (Front-Left/Front-Right)
DSD data left channel
Trap value in power-on reset:
1:manufactory test mode
0:normal operation
218 ASDATA1
I/O
Audio serial data 1 (Left-Surround/Right-Surround)
DSD data right channel
Trap value in power-on reset:
1:manufactory test mode
0:normal operation
While only 2 channels output:
GPO
Summary of Contents for DV-2850-S
Page 34: ...DV 2850 S 34 1 2 3 4 1 2 3 4 C D F A B E ...
Page 38: ...DV 2850 S 38 1 2 3 4 1 2 3 4 C D F A B E SIDE B A CP4003 CP8001 ...
Page 43: ...DV 2850 S 43 5 6 7 8 5 6 7 8 C D F A B E C658 C605 C604 SIDE B B C G CP603 CP601 CP605 IC651 ...
