1
8
2
DJM-900NXS
1
2
3
4
A
B
C
D
E
F
1
2
3
4
DIR_ADC_DAC_RESET
V
: 1.0
V
/div. H: 1 mS/div.
G
MAIN ASSY
1-28
DIT_RST
V
: 1.0
V
/div. H: 1 mS/div.
1-29
CPU_MUTE
V
: 1.0
V
/div. H: 1 mS/div.
1-38
CPU_RESET
V
: 1.0
V
/div. H: 1 mS/div.
1-39
96k_CLK_AIN
V
: 1.0
V
/div. H: 2
μ
S/div.
1-44
96k_CLK_ADDA
V
: 1.0
V
/div. H: 2
μ
/div.
1-49
SUB_SH_RST
V
: 1.0
V
/div. H: 1 mS/div.
1-43
6M_CLK_ADDA
V
: 1.0
V
/div. H: 50 nS/div.
1-48
FPGA_RST
V
: 1.0
V
/div. H: 1 mS/div.
1-30
24M_CLK_USB
V
: 1.0
V
/div. H: 10 nS/div.
1-35
20M_CLK_MAIN
V
: 1.0
V
/div. H: 20 nS/div.
1-40
20M_CLK_SH
V
: 1.0
V
/div. H: 20 nS/div.
1-41
6M_CLK_AIN
V
: 1.0
V
/div. H: 50 nS/div.
1-45
24M_CLK_AIN
V
: 1.0
V
/div. H: 10 nS/div.
1-46
24M_CLK_FPGA
V
: 1.0
V
/div. H: 10 nS/div.
1-53
SH_FPGA_DONE
V
: 1.0
V
/div. H: 1 mS/div.
1-54
USB_RESET
V
: 1.0
V
/div. H: 1 mS/div.
1-36
24.5764_CLK
V
: 1.0
V
/div. H: 20 nS/div.
1-42
24M_CLK_ADDA
V
: 1.0
V
/div. H: 10 nS/div.
1-47
24.5M_CLK_DSP
V
: 1.0
V
/div. H: 10 nS/div.
1-59
Summary of Contents for DJM-900NXS
Page 10: ...10 DJM 900NXS 1 2 3 4 A B C D E F 1 2 3 4 2 2 PANEL FACILITIES ...
Page 11: ...11 DJM 900NXS 5 6 7 8 5 6 7 8 A B C D E F ...
Page 12: ...12 DJM 900NXS 1 2 3 4 A B C D E F 1 2 3 4 ...
Page 15: ...15 DJM 900NXS 5 6 7 8 5 6 7 8 A B C D E F ...
Page 20: ...20 DJM 900NXS 1 2 3 4 A B C D E F 1 2 3 4 4 3 DSP BLOCK DIAGRAM ...
Page 21: ...21 DJM 900NXS 5 6 7 8 5 6 7 8 A B C D E F ...
Page 87: ...87 DJM 900NXS 5 6 7 8 5 6 7 8 A B C D E F ...
Page 189: ...189 DJM 900NXS 5 6 7 8 5 6 7 8 A B C D E F ...
Page 192: ...192 DJM 900NXS 1 2 3 4 A B C D E F 1 2 3 4 A SIDE B A INPUT ASSY CN4003 CN4002 CN5001 CN5401 ...