Pioneer DEQ-P9, Service Manual

Page: 42 / 48

42
DEQ-P9
Periodical communications with DSP
DSP error verification(under normal conditions)
DSP error verification(under continued abnormal conditions)
The communications are performed with the DSP IC at 4 ms intervals (see upper left figure). The determination on
whether the DSP IC is operating normally or not, is made by monitoring the DSPACK(Pin66) and DSPERR(Pin65).
Under normal conditions, the DSPACK(Pin66) will fall to LOW after counting 9 clock cycles of the DSPCK(Pin26) (see
upper right figure). By determining which of the DSPCS1-3(Pin61/62/63) is LOW during that time, we can find out
which IC is engaged in communications. When the DSPACK(Pin66) does not become LOW, then the IC of that DSPACK
(Pin66) may be faulty or abnormal.
An error will occur with the DSPERR(Pin65), when it is LOW. The DSPERR(Pin65) may become LOW during initializa-
tion, but an error occurs at the DSP when it is LOW during a periodical communication. An error is relayed in the order
of CHIP1
→
CHIP3
→
CHIP2 of the DSP, so please determine at which IC the error is occurring.
Others
When LRCK§BCK and DATA are being output from DSP IC in a normal manner, please verify the output of the DF IC.
When a digital waveform is being output from the DF IC, then please check the DAC IC. When an analog waveform is
being output from the DAC IC, then please check the EVOL IC.
DSPRST(Pin67)
Approx.3
sec.
intervals
4 ms intervals(communications)