DEH-P5900MP/XU/EW5
59
5
7
8
5
6
7
8
C
D
F
A
B
E
PEG284A
50
81
100
31
80
1
30
51
Format
Meaning
C
CMOS
N
Nch open drain
Pin No.
Pin Name
I/O
Function and Operation
65
66
67
68
69-73
74
75
76-80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
ce@
CE1
TUNPCK
TUNPDI
NC
rck
ldet
NC
rds-lock
RDS-DATA
rds-hslk
NC
RECIVE
TUNPDO
NC
TESTIN
RGBCK
rgbst
rgbdt
SSENS
CSENS
KEYAD
NC
AVSS
SL
VREF
AVCC
NC
O
O
O
I
I
I
I
O
O
I
O
O
O
I
I
I
Format
C
C
C
C
C
C
C
C
C
C
C
TUNER : Chip enable output(EEPROM)
TUNER : Chip enable output(PLL)
TUNER : Clock output(PLL)
TUNER : Data input(PLL)
Not used
RDS : Clock interrupt
RDS : PLL lock detection interrupt
Not used
RDS : Lock signal input
RDS : Data input
RDS57K input(connected to HSLK)
Not used
For operation check of RDS circuit
TUNER : Data output(PLL)
Not used
Test program input
RGB DAC clock output
RGB DAC strobe output
RGB DAC strobe output
Source key
Flap opening-and-closing sense input
Wired remote control AD input
Not used
A/D converter GND(Connected to VSS)
Signal level input(Field intensity)
A/D converter reference voltage input
A/D converter power supply input terminal(Connected to VCC)
Not used
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9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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