Pioneer AVD-505, Service Manual

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AVD-505
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Pin Functions (LZ9GF16)
Pin No. Pin Name I/O Function and Operation
1 VIN I Vertical synchronizing signal input (positive electrode)
2 CVOP O Vertical synchronizing countdown output
3 CVIN I Vertical synchronizing countdown input
4 DVOP O Digital separation vertically synchronized output (positive electrode)
5 FRPT O Signal output for common electrode drive signal polarity inversion
6 GPS O Signal output for gate power supply
7 GND Power supply ground
8 EXCL I/O Clock signal input/output
9 SYNI I Composite synchronizing signal input
10
hsy
I/O Horizontal synchronizing signal input/output (negative electrode)
11
vsy
I/O Vertical synchronizing signal input/output (negative electrode)
12 DIS O Source driver control signal output
13 TESTO O Test monitor signal output
14 NTPC I Terminal for setting NTSC/PAL H:NTSC L:MBK-PAL
15 VRVC I Terminal for setting vertical scanning direction H:Normal L:Reverse
16 HRVC I Terminal for setting horizontal scanning direction H:Normal L:Reverse
17 CHK O Control signal output for backlight PWM Light adjuster
18 TESTI I Input terminal for testing
19 TESTO O Test monitor signal output
20 VR O Vertical scanning direction setting output for gate driver
21 SPS O Gate driver start signal output
22 CLS O Gate driver clock signal output
23 LOWO O Gate driver control signal output
24 CTR O Source driver control signal output
25 SPD O Source driver start signal output
26 CLD O Source driver clock signal output
27 OSCO O Clock oscillation circuit output
28 OSCI I/O Clock oscillation circuit input/output
29 SAMO O Source driver control signal output
30 VDD Power supply (+5V)
31 GND Power supply ground
32 TESTI I Input terminal for testing
33 LOWI I Initial reset signal input
34 FRPV O Signal output for video signal polarity inversion
35 RESH I Signal output reset terminal for source driver H:Normal L:Forced reset
36 PDP O PLL Phase comparison circuit output
37 RESV I Signal output reset terminal for gate driver H:Normal L:Forced reset
38,39 TESTI I Input terminal for testing
40 IHR O Source driver control signal output
41 HR O Source driver control signal output
42 CLOC I Terminal for setting EXCL (clock signal) output
H:L-Level output L:Clock output
43 CLKC I Terminal for setting clock · synchronizing signal input/output
H:EXCL ·
hsy
·
vsy
signal output L:EXCL ·
hsy
·
vsy
signal input
44 TESTI I Input terminal for testing
45 SAMC I Terminal for setting sampling mode
H:Non-simultaneous sampling L:Simultaneous sampling
46 BLKI I PLL phase comparison input Input BLKO delayed signal
47 BLKO O Output for PLL phase comparison signal Input into BLKI following delay
48 SYNO O Composite synchronizing signal output for vertical synchronized
separation (positive electrode)