Carrier Board phyCORE-PXA270
5.2.2
External Data and Address Bus
The data and address bus on the phyCORE-PXA270 operates with a
clock frequency of 100 MHz, therefore it must be decoupled for
external use. All components on the Carrier Board except the Control
PLD are connected to the decoupled data and address bus. The driver
ICs are controlled by the PLD at U7 depending on the state of the
corresponding Chip Select signal.
J15
J27
J3
U12
D7
U13
R60
U2
U22
U21
XT2
U10
J10
PXA270
XT1
U3
L1
J23
R103
J9
J21
Q6
J6
J32
X2
D6
Q1
U7
J30
R13
J16
J17
J29
U5
XT4
J26
U15
J11
U20
J2
J28
J19
J20
D0-31
A0-25
CTRL
xD0-31
xA0-25
xCTRL
Figure 13: Decoupling the Data and Address Bus
30
©
PHYTEC Meßtechnik GmbH 2006 L-668e_1
Summary of Contents for phyCORE-PXA270
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