Phytec phyCORE-OMAP44 Series, Hardware Manual

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phyCORE-OMAP44xx Part I: PCM-049/phyCORE-OMAP44xx System on Module
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1.8.2 USB OTG Interface
The phyCORE-OMAP44xx provides a high speed USB OTG interface which uses the OMAP44xx embedded HS USB
OTG PHY. Since the integrated PHY does not support the OTG features ID pin detection and V
BUS
detection, these
features are implemented using the on-board PMIC TWL6030. An external USB Standard-A (for USB host), USB
Standard-B (for USB device), or USB mini-AB (for USB OTG) connector is all that is needed to interface the
phyCORE-OMAP44xx USB OTG functionality. The applicable interface signals can be found on the phyCORE-
Connector as shown in
Table 18 .
1.8.3 USB Host Transceiver (U8)
The phyCORE-OMAP44xx is populated with an SMSC USB3320 USB High-Speed transceiver (U8) supporting the
high speed data rates of the OMAP44xx. The USB3320 is connected to the first Host Controller's ULPI interface
(USBB1) on the OMAP44xx. An external USB Standard-A (for USB host) connector is all that is needed to
interface the phyCORE-OMAP44xx USB Host functionality. The applicable interface signals (D+/D-/ PWR/OC)
can be found on the phyCORE-Connector. Since the USB3320 doesn't have an overcurrent input, this signal is
connected to GPIO 120 of the OMAP44xx.
The USB3320 USB High-Speed transceiver (U8) is supplied by the switchable 3.3 V voltage domain (VCC_3V3_S)
which is also available at the reference voltage output pin X1D23 on the phyCORE-Connector.
To fully support V
BUS
power control using an external V
BUS
switch the phyCORE-OMAP44xx provides the control
signal X_USBB1_PWR (X1D22). It can be used to switch an external V
BUS
power supply and is derived from the
USB High-Speed transceiver's CPEN signal
1
(refer to the USB3320 datasheet for more information).
Pin # Signal I/O SL Description
X1C19 X_USB_OTG_DP I/O USB USB OTG data plus
X1C20 X_USB_OTG_DM I/O USB USB OTG data minus
X1C22 X_PMIC_USB_OTG_ID I/O USB USB OTG connector
identification signal
X1C23 X_PMIC_USB_OTG_VBUS I USB USB OTG V
BUS
detection
input
Table 18:
Location of the USB OTG Signals
Pin # Signal I/O SL Description
X1D18 X_USBB1_OC_GPIO_120 I 1.8 V USB Host overcurrent
signal input
X1D20 X_USBB1_DP I/O USB USB Host data plus
X1D21 X_USBB1_DM I/O USB USB Host data minus
X1D22 X_USBB1_PWR O 3.3 V
(VCC_3V3_S) External USB supply
voltage (5 V) enable
(to control an external
power switch)
Table 19:
Location of the USB Host Signals
1. Removing R34 and mounting Q5 and R21 allows to also generate this signal by GPIO 119 of the OMAP44xx if needed. Please contact
our sales team for more details.