PHYTEC
Page 20
The following is an example of the pin muxing of the UART1 device in
:
imx8mp-phyboard-pollux.dtsi
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154
MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154
>;
};
The first part of the string MX8MP_IOMUXC_SAI2_TXC__CAN1_RX names the pad (in this example
). The second part of the string (CAN1
SAI2_TXC
_RX
) is the desired muxing option for this pad.
The pad setting value (hex value on the right) defines different modes of the pad. For example, if internal pull resistors are activated or not. In this case,
the internal resistors are disabled.
Network
phyCORE-i.MX8MP provides two ethernet interfaces. In the ALPHA1 release, only the EQOS IP core with the DP83867 populated on the carrier board is
functional. All interfaces offer a standard
network port that can be programmed using the BSD socket interface. The whole network configuration is
Linux
handled by the
daemon. The relevant configuration files can be found on the target in
and also in the BSP in meta-
systemd-networkd
/lib/systemd/network/
yogurt/recipes-core/systemd/system-machine-units.
IP addresses can be configured within
files.
*.network
phyBOARD-Pollux DT,
:
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux.dtsi
