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5 Hardware Interface
Level-controlled Exposure
In the level-controlled trigger mode, the exposure time is defined by the pulse width of the
external trigger signal. For an active high trigger signal, the image acquisition begins with the
rising edge and stops with the falling edge of the external trigger signal. Then the image is
read out. After that, the sensor returns to the idle state and the camera module waits for a
new trigger pulse (see Fig. 5.8). The data is output on the rising edge of the pixel clock, the
handshaking signals
FRAME_VALID
(
FVAL
) and
LINE_VALID
(
LVAL
) mask valid image information. The
signal
SHUTTER
in Fig. 5.8 indicates the active integration phase of the sensor and is shown for
clarity only.
Level-controlled exposure is not supported in simultaneous readout mode.
P C L K
S H U T T E R
F V A L
L V A L
D V A L
D A T A
L i n e p a u s e
L i n e p a u s e
L i n e p a u s e
F i r s t L i n e
L a s t L i n e
E x p o s u r e
T i m e
F r a m e T i m e
E X S Y N C
C P R E
Figure 5.8: Trigger timing diagram for level controlled exposure
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Summary of Contents for OEM-D1024E
Page 1: ...User Manual OEM D752E and OEM D1024E CMOS Sensor Module Series MAN032 04 2012 V1 2...
Page 2: ......
Page 4: ...2...
Page 10: ...2 Introduction and Motivation 8...
Page 18: ...3 OEM Specification 16...
Page 46: ...4 Functionality 44...
Page 66: ...7 Warranty 64...
Page 68: ...8 References 66...