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Philips UDA1334BT Datasheet Download Page 16

2002 May 22

16

Philips Semiconductors

Product specification

Low power audio DAC

UDA1334BT

15 APPLICATION INFORMATION

handbook, full pagewidth

MGU677

47 

Ω

R5

UDA1334BT

6

SYSCLK

system

clock

1

BCK

2

WS

3

DATAI

14

VOUTL

R3

100 

Ω

R1
220 k

Ω

16

VOUTR

R4

100 

Ω

R2
220 k

Ω

7

SFOR1

11

SFOR0

9

DEEM

10

PCS

8

MUTE

47 

µ

F

(16 V)

C4

47 

µ

F

(16 V)

C3

left
output

right
output

12

Vref(DAC)

C7
47

 µ

F

(16 V)

C8
100

 

nF

(63 V)

4

5

VDDD

VSSD

R6
1 

Ω

digital

supply voltage

C6

15

13

VSSA

VDDA

R7
1 

Ω

C9

47

 µ

F

(16 V)

C10

100 nF

(63 V)

100 nF

(63 V)

analog

supply voltage

C5

47

 µ

F

(16 V)

C1

10 nF
(63 V)

10 nF
(63 V)

C2

Fig.8  Typical application diagram.

Summary of Contents for UDA1334BT

Page 1: ...DATA SHEET Product specification 2002 May 22 INTEGRATED CIRCUITS UDA1334BT Low power audio DAC ...

Page 2: ... 8 6 Feature settings 8 6 1 Digital interface format select 8 6 2 Mute control 8 6 3 De emphasis control 8 6 4 Power control and sampling frequency select 9 LIMITING VALUES 10 HANDLING 11 THERMAL CHARACTERISTICS 12 QUALITY SPECIFICATION 13 DC CHARACTERISTICS 14 AC CHARACTERISTICS 14 1 2 0 V supply voltage 14 2 3 0 V supply voltage 14 3 Timing 15 APPLICATION INFORMATION 16 PACKAGE OUTLINE 17 SOLDER...

Page 3: ... emphasis for 44 1 kHz sampling rate Mute function 1 4 Advanced audio configuration High linearity wide dynamic range and low distortion Standby or Sleep mode in which the DAC is powered down 2 APPLICATIONS This audio DAC is excellently suitable for digital audio portable application such as portable MD MP3 and DVD players 3 GENERAL DESCRIPTION The UDA1334BT supports the I2S bus data format with w...

Page 4: ...s noise to signal ratio fs 44 1 kHz at 0 dB 80 dB fs 44 1 kHz at 60 dB A weighted 37 dB fs 96 kHz at 0 dB 75 dB fs 96 kHz at 60 dB A weighted 35 dB S N signal to noise ratio fs 44 1 kHz code 0 A weighted 97 dB fs 96 kHz code 0 A weighted 95 dB αcs channel separation 100 dB Digital to analog converter VDDA VDDD 3 0 V Vo rms output voltage RMS value at 0 dB FS digital input note 1 900 mV THD N S tot...

Page 5: ...A1334BT 6 BLOCK DIAGRAM handbook full pagewidth MGU676 DAC UDA1334BT NOISE SHAPER INTERPOLATION FILTER DE EMPHASIS 14 15 DAC 6 DIGITAL INTERFACE 16 3 2 1 4 5 11 7 13 12 VOUTR BCK VSSA WS VOUTL DATAI VDDA VDDD Vref DAC VSSD SFOR0 SYSCLK 8 MUTE 9 DEEM 10 PCS SFOR1 Fig 1 Block diagram ...

Page 6: ...pply voltage VSSD 5 digital ground pad digital ground SYSCLK 6 5 V tolerant digital input pad note 1 system clock input SFOR1 7 5 V tolerant digital input pad note 1 serial format select 1 MUTE 8 5 V tolerant digital input pad note 1 mute control DEEM 9 5 V tolerant digital input pad note 1 de emphasis control PCS 10 3 level input pad note 2 power control and sampling frequency select SFOR0 11 dig...

Page 7: ...ampling frequency should be limited to 55 kHz 2 Not supported in the low sampling frequency mode An example is given in Table 2 for a 12 228 MHz system clock input Table 2 Example using a 12 228 MHz system clock Note 1 This mode can only be supported for power supply voltages down to 2 4 V For lower voltages in 192fs mode the sampling frequency should be limited to 55 kHz 8 2 Interpolation filter ...

Page 8: ...ltage signal capable of driving a line output The output voltage of the FSDAC scales proportionally with the power supply voltage 8 5 Power on reset The UDA1334BT has an internal Power on reset circuit see Fig 3 which resets the test control block The reset time see Fig 4 is determined by an external capacitor which is connected between pin Vref DAC and ground The reset time should be at least 1 µ...

Page 9: ...trol Remark the de emphasis function in only supported in the normal operating mode not in the low sampling frequency mode 8 6 4 POWER CONTROL AND SAMPLING FREQUENCY SELECT Pin PCS is a 3 level pin and is used to set the mode of the UDA1334BT The definition is given in Table 7 Table 7 PCS function definition The low sampling frequency mode is required to have a higher oversampling rate in the nois...

Page 10: ...through the pdf in the Acrobat reader white to force landscape pages to be handbook full pagewidth MGS752 16 B5 B6 B7 B8 B9 B10 LEFT LSB JUSTIFIED FORMAT 24 BITS WS BCK DATA RIGHT 15 18 17 20 19 22 21 23 24 2 1 B3 B4 MSB B2 B23 LSB 16 B5 B6 B7 B8 B9 B10 15 18 17 20 19 22 21 23 24 2 1 B3 B4 MSB B2 B23 LSB 16 MSB B2 B3 B4 B5 B6 LEFT LSB JUSTIFIED FORMAT 20 BITS WS BCK DATA RIGHT 15 18 17 20 19 2 1 B...

Page 11: ... ground pins VSSA and VSSD unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN MAX UNIT VDD supply voltage note 1 4 0 V Txtal max maximum crystal temperature 150 C Tstg storage temperature 65 125 C Tamb ambient temperature 40 85 C Ves electrostatic handling voltage human body model 2000 2000 V machine model 200 200 V Isc DAC short circuit current of DAC note 2 output short circuited to VSSA...

Page 12: ...ltage clock running 250 µA no clock running 20 µA Sleep mode at 3 0 V supply voltage clock running 375 µA no clock running 30 µA Digital input pins note 2 VIH HIGH level input voltage at 2 0 V supply voltage 1 3 3 3 V at 3 0 V supply voltage 2 0 5 0 V VIL LOW level input voltage at 2 0 V supply voltage 0 5 0 5 V at 3 0 V supply voltage 0 5 0 8 V ILI input leakage current 1 µA Ci input capacitance ...

Page 13: ... 0 dB 80 dB fs 44 1 kHz at 60 dB A weighted 37 dB fs 96 kHz at 0 dB 75 dB fs 96 kHz at 60 dB A weighted 35 dB S N signal to noise ratio fs 44 1 kHz code 0 A weighted 97 dB fs 96 kHz code 0 A weighted 95 dB αcs channel separation 100 dB PSRR power supply rejection ratio fripple 1 kHz Vripple 30 mV p p 60 dB SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT DAC Vo rms output voltage RMS value at 0 dB FS ...

Page 14: ...cycle time fsys 256fs 35 88 780 ns fsys 384fs 23 59 520 ns fsys 512fs 17 44 390 ns tCWH system clock HIGH time fsys 19 2 MHz 0 3Tsys 0 7Tsys ns fsys 19 2 MHz 0 4Tsys 0 6Tsys ns tCWL system clock LOW time fsys 19 2 MHz 0 3Tsys 0 7Tsys ns fsys 19 2 MHz 0 4Tsys 0 6Tsys ns Reset timing treset reset time 1 µs Serial interface timing see Fig 7 fBCK bit clock frequency 64fs Hz tBCKH bit clock HIGH time 5...

Page 15: ...specification Low power audio DAC UDA1334BT handbook full pagewidth MGR984 Tsys tCWH tCWL Fig 6 System clock timing handbook full pagewidth MGL880 tf th WS tsu WS tsu DATAI th DATAI tBCKH tBCKL Tcy BCK tr WS BCK DATAI Fig 7 Serial interface timing ...

Page 16: ...DATAI 14 VOUTL R3 100 Ω R1 220 kΩ 16 VOUTR R4 100 Ω R2 220 kΩ 7 SFOR1 11 SFOR0 9 DEEM 10 PCS 8 MUTE 47 µF 16 V C4 47 µF 16 V C3 left output right output 12 Vref DAC C7 47 µF 16 V C8 100 nF 63 V 4 5 VDDD VSSD R6 1 Ω digital supply voltage C6 15 13 VSSA VDDA R7 1 Ω C9 47 µF 16 V C10 100 nF 63 V 100 nF 63 V analog supply voltage C5 47 µF 16 V C1 10 nF 63 V 10 nF 63 V C2 Fig 8 Typical application diag...

Page 17: ...45 1 25 0 25 0 49 0 36 0 25 0 19 10 0 9 8 4 0 3 8 1 27 6 2 5 8 0 7 0 6 0 7 0 3 8 0 o o 0 25 0 1 DIMENSIONS inch dimensions are derived from the original mm dimensions Note 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included 1 0 0 4 SOT109 1 97 05 22 99 12 27 076E07 MS 012 0 069 0 010 0 004 0 057 0 049 0 01 0 019 0 014 0 0100 0 0075 0 39 0 38 0 16 0 15 0 050 1 05 0 041 0 244...

Page 18: ...etting can present major problems To overcome these problems the double wave soldering method was specifically developed If wave soldering is used the following conditions must be observed for optimal results Use a double wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave For packages with leads on two sides and a pitch e larger than or eq...

Page 19: ...ottom side the solder cannot penetrate between the printed circuit board and the heatsink On versions with the heatsink on the top side the solder might be deposited on the heatsink surface 4 If wave soldering is considered then the package must be placed at a 45 angle to the solder wave direction The package footprint must incorporate solder thieves downstream and at the side corners 5 Wave solde...

Page 20: ...es definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values...

Page 21: ...2002 May 22 21 Philips Semiconductors Product specification Low power audio DAC UDA1334BT NOTES ...

Page 22: ...2002 May 22 22 Philips Semiconductors Product specification Low power audio DAC UDA1334BT NOTES ...

Page 23: ...2002 May 22 23 Philips Semiconductors Product specification Low power audio DAC UDA1334BT NOTES ...

Page 24: ......

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