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Philips TDA8950 Product Data Sheet Download Page 31

TDA8950_2

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 02 — 11 June 2009

31 of 39

NXP Semiconductors

TDA8950

2

×

 150 W class-D power amplifier

V

P

 =

±

35 V, f

osc

 = 325 kHz, V

i

 = 2 V (RMS).

(1) 8

Ω

.

(2) 6

Ω

.

(3) 4

Ω

.

Fig 27. Mute attenuation as a function of frequency

001aai713

f

i

 (Hz)

10

10

5

10

4

10

2

10

3

−

70

−

80

−

60

−

50

α

mute

(dB)

−

90

(1)
(2)
(3)

Summary of Contents for TDA8950

Page 1: ...ed Load BTL amplifier n High output power in typical applications u SE 2 150 W RL 4 Ω VP 37 V u SE 2 170 W RL 4 Ω VP 39 V u SE 2 100 W RL 6 Ω VP 37 V u BTL 1 300 W RL 8 Ω VP 37 V n Low noise n Smooth pop noise free start up and switch off n Zero dead time switching n Fixed frequency n Internal or external clock n High efficiency n Low quiescent current n Advanced protection strategy voltage protec...

Page 2: ...tection supply voltage Standby Mute modes VDD VSS 85 90 V Iq tot total quiescent current Operating mode no load no filter no RC snubber network connected 50 75 mA Stereo SE configuration Po output power Tj 85 C LLC 22 µH CLC 680 nF see Figure 10 3 THD N 10 RL 4 Ω VP 39 V 170 W THD N 0 5 RL 4 Ω VP 37 V 100 W THD N 10 RL 4 Ω VP 37 V 150 W THD N 10 RL 6 Ω VP 37 V 100 W Mono BTL configuration Po outpu...

Page 3: ...TDA8950TH TDA8950J BOOT1 DRIVER LOW SWITCH1 CONTROL AND HANDSHAKE PWM MODULATOR MANAGER OSCILLATOR TEMPERATURE SENSOR CURRENT PROTECTION VOLTAGE PROTECTION STABI MODE INPUT STAGE mute 9 3 8 2 IN1M IN1P 22 15 21 14 20 13 17 11 16 10 15 9 VSSP2 VSSP1 DRIVER HIGH DRIVER LOW SWITCH2 CONTROL AND HANDSHAKE PWM MODULATOR 11 5 n c 7 1 OSC 2 19 SGND 6 23 MODE INPUT STAGE mute 5 22 4 21 IN2M IN2P 19 24 17 V...

Page 4: ...n configuration TDA8950J TDA8950TH VSSD VSSA VDDP2 SGND BOOT2 VDDA OUT2 IN2M VSSP2 IN2P n c MODE STABI OSC VSSP1 IN1P OUT1 IN1M BOOT1 n c VDDP1 n c PROT n c 001aah654 24 23 22 21 20 19 18 17 16 15 14 13 11 12 9 10 7 8 5 6 3 4 1 2 TDA8950J OSC IN1P IN1M n c n c n c PROT VDDP1 BOOT1 OUT1 VSSP1 STABI VSSP2 OUT2 BOOT2 VDDP2 VSSD VSSA SGND VDDA IN2M IN2P MODE 001aah655 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ...

Page 5: ...scription Symbol Pin Description TDA8950TH TDA8950J VSSA 1 18 negative analog supply voltage SGND 2 19 signal ground VDDA 3 20 positive analog supply voltage IN2M 4 21 channel 2 negative audio input IN2P 5 22 channel 2 positive audio input MODE 6 23 mode selection input Standby Mute or Operating mode OSC 7 1 oscillator frequency adjustment or tracking input IN1P 8 2 channel 1 positive audio input ...

Page 6: ...E Standby mode featuring very low quiescent current Mute mode the amplifier is operational but the audio signal at the output is suppressed by disabling the voltage to current VI converter input stages Operating mode the amplifier is fully operational de muted and can deliver an output signal A slowly rising voltage should be applied e g via an RC network to pin MODE to ensure pop noise free start...

Page 7: ...reaches the Operating mode level see Table 8 but not earlier than 150 ms after switching to Mute To start up pop noise free it is recommended that the time constant applied to pin MODE be at least 350 ms for the transition between Mute and Operating modes Lower diagram When switching directly from Standby to Operating mode there is a delay of 100 ms before the outputs start switching The audio sig...

Page 8: ...nown as beat tones can be generated 8 3 Protection The following protection circuits are incorporated into the TDA8950 Thermal protection Thermal FoldBack TFB OverTemperature Protection OTP OverCurrent Protection OCP Window Protection WP Supply voltage protection UnderVoltage Protection UVP OverVoltage Protection OVP UnBalance Protection UBP How the device reacts to a fault conditions depends on w...

Page 9: ... conditions and other overcurrent conditions such as a dynamic impedance drop at the loudspeaker The impedance threshold Zth depends on the supply voltage How the amplifier reacts to a short circuit depends on the short circuit impedance Short circuit impedance Zth the amplifier limits the maximum output current to IORM but the amplifier does not shut down the PWM outputs Effectively this results ...

Page 10: ...ures the TDA8950 amplifier is fully protected against short circuit conditions while avoiding audio holes 1 VP is the supply voltage on pins VDDP1 VDDP2 and VDDA 2 OVP can be triggered by supply pumping see Section 13 6 8 3 3 Window Protection WP Window Protection WP checks the conditions at the output terminals of the power stage and is activated During the start up sequence when the TDA8950 is s...

Page 11: ...he amplifier shuts down completely only if the short circuit impedance is below the impedance threshold Zth see Section 8 3 2 In all other cases current limiting results in a clipped output signal 3 Fault condition detected during any Standby to Mute transition or during a restart after OCP has been activated short circuit to one of the supply lines 8 4 Differential audio inputs The audio inputs a...

Page 12: ... limiting 9 2 A Tstg storage temperature 55 150 C Tamb ambient temperature 40 85 C Tj junction temperature 150 C VMODE voltage on pin MODE referenced to SGND 0 6 V VOSC voltage on pin OSC 0 SGND 6 V VI input voltage referenced to SGND pin IN1P IN1M IN2P and IN2M 5 5 V VPROT voltage on pin PROT referenced to voltage on pin VSSD 0 12 V VESD electrostatic discharge voltage Human Body Model HBM 2000 2...

Page 13: ...Hz Tamb 25 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Supply VP 1 supply voltage Operating mode 2 12 5 30 40 V VP ovp overvoltage protection supply voltage Standby Mute modes VDD VSS 85 90 V VP uvp undervoltage protection supply voltage VDD VSS 20 25 V VP ubp unbalance protection supply voltage 3 33 Iq tot total quiescent current Operating mode no load no filter no R...

Page 14: ...avior of mode selection pin MODE Standby Mute On 5 5 coa021 VMODE V 4 2 3 0 2 2 0 8 0 VO V VO offset mute VO offset on slope is directly related to the time constant of the RC network on the MODE pin Table 9 Dynamic characteristics VP 1 35 V Tamb 25 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Internal oscillator fosc typ typical oscillator frequency ROSC 30 0 kΩ 290 3...

Page 15: ...put power Tj 85 C LLC 22 µH CLC 680 nF see Figure 10 3 THD N 10 RL 4 Ω VP 39 V 170 W THD N 0 5 RL 4 Ω VP 37 V 100 W THD N 10 RL 4 Ω VP 37 V 150 W THD N 10 RL 6 Ω VP 37 V 100 W THD total harmonic distortion Po 1 W fi 1 kHz 4 0 05 Po 1 W fi 6 kHz 4 0 05 Gv cl closed loop voltage gain 29 30 31 dB SVRR supply voltage ripple rejection between pins VDDPn and SGND Operating mode fi 100 Hz 5 90 dB Operati...

Page 16: ...kHz Table 11 Dynamic characteristics VP 1 35 V RL 8 Ω fi 1 kHz fosc 345 kHz RsL 2 0 1 Ω Tamb 25 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Po output power Tj 85 C LLC 22 µH CLC 680 nF see Figure 10 3 THD N 10 RL 8 Ω VP 39 V 340 W THD N 0 5 RL 8 Ω VP 37 V 200 W THD N 10 RL 8 Ω VP 37 V 300 W THD total harmonic distortion Po 1 W fi 1 kHz 4 0 05 Po 1 W fi 6 kHz 4 0 05 Gv...

Page 17: ...w dV dt for the DC output offset voltage ensuring a pop noise free transition between Mute and Operating modes A time constant of 500 ms is sufficient to guarantee pop noise free start up see Figure 4 Figure 5 and Figure 8 for more information 13 3 Estimating the output power 13 3 1 Single Ended SE Maximum output power 1 Maximum output current is internally limited to 9 2 A 2 Where Po 0 5 output p...

Page 18: ...ernal clock To ensure duty cycle independent operation the external clock frequency is divided by two internally The external clock frequency is therefore twice the internal clock frequency typically 2 350 kHz 700 kHz If several Class D amplifiers are used in a single application it is recommended that all the devices run at the same switching frequency This can be achieved by connecting the OSC p...

Page 19: ...and total thermal resistance from junction to ambient 5 Power dissipation P is determined by the efficiency of the TDA8950 Efficiency measured as a function of output power is given in Figure 20 Power dissipation can be derived as a function of output power as shown in Figure 19 1 Rth j a 5 K W 2 Rth j a 10 K W 3 Rth j a 15 K W 4 Rth j a 20 K W 5 Rth j a 35 K W Fig 9 Derating curves for power diss...

Page 20: ...lues are illustrated in Figure 9 A maximum junction temperature Tj 150 C is taken into account The maximum allowable power dissipation for a given heatsink size can be derived or the required heatsink size can be determined at a required power dissipation level see Figure 9 13 6 Pumping effects In a typical stereo single ended configuration the TDA8950 is supplied by a symmetrical supply voltage e...

Page 21: ... 7 Application schematic Notes on the application schematic Connect a solid ground plane around the switching amplifier to avoid emissions Place 100 nF capacitors as close as possible to the TDA8950 power supply pins Connect the heatsink to the ground plane or to VSSPn using a 100 nF capacitor Use a thermally conductive electrically non conductive Sil Pad between the TDA8950 heat spreader and the ...

Page 22: ...N2 IN1M SGND 2 3 19 22 21 20 18 470 nF 470 nF CIN CIN IN2P IN2M 470 nF 470 nF CIN 220 nF VDDA VSSA 17 7 VSSP VDDA VSSA PROT 13 14 15 VSSP VSSP2 OUT2 BOOT2 16 VDDP VDDP2 VSSD CVDDA 220 nF CVSSA 100 nF CVDDP 15 nF CBO 100 nF CVSSP 100 nF CVP VSSP VSSP VSSP VDDP VDDP VDDP 11 VSSP1 8 VDDP1 23 MODE mode control 1 OSC 6 4 n c 5 n c n c 100 nF CVDDP 100 nF CVSSP 100 nF CVP CPROT 1 VSSA 12 STABI CSTAB 470...

Page 23: ...Ω SE configuration 1 fi 6 kHz 2 fi 1 kHz 3 fi 100 Hz Fig 11 THD N as a function of output power SE configuration with 2 4 Ω load VP 35 V fosc 345 kHz 2 6 Ω SE configuration 1 fi 6 kHz 2 fi 1 kHz 3 fi 100 Hz Fig 12 THD N as a function of output power SE configuration with 2 6 Ω load 010aaa553 10 1 10 2 1 10 THD 10 3 Po W 10 2 103 102 10 1 1 10 1 2 3 010aaa554 10 1 10 2 1 10 THD 10 3 Po W 10 2 103 1...

Page 24: ...iguration 1 fi 6 kHz 2 fi 1 kHz 3 fi 100 Hz Fig 13 THD N as a function of output power BTL configuration with 1 8 Ω load VP 35 V fosc 345 kH 2 4 Ω SE configuration 1 Po 1 W 2 Po 10 W Fig 14 THD N as a function of frequency SE configuration with 2 4 Ω load 001aai423 10 1 10 2 1 10 THD 10 3 PO W 10 2 103 102 10 1 1 10 1 2 3 001aai424 10 1 10 2 1 10 THD 10 3 fi Hz 10 105 104 102 103 1 2 ...

Page 25: ... Ω SE configuration 1 Po 1 W 2 Po 10 W Fig 15 THD N as a function of frequency SE configuration with 2 6 Ω load VP 35 V fosc 345 kHz 1 8 Ω BTL configuration 1 Po 1 W 2 Po 10 W Fig 16 THD N as a function of frequency BTL configuration with 1 8 Ω load 001aai701 10 1 10 2 1 10 THD 10 3 fi Hz 10 105 104 102 103 1 2 001aai702 10 1 10 2 1 10 THD 10 3 fi Hz 10 105 104 102 103 1 2 ...

Page 26: ...ion 1 W and 10 W respectively Fig 17 Channel separation as a function of frequency SE configuration with 2 4 Ω load VP 35 V fosc 345 kHz 2 6 Ω SE configuration 1 W and 10 W respectively Fig 18 Channel separation as a function of frequency SE configuration with 2 6 Ω load 001aai703 fi Hz 10 105 104 102 103 60 40 80 20 0 αcs dB 100 001aai704 fi Hz 10 105 104 102 103 60 40 80 20 0 αcs dB 100 ...

Page 27: ...on 3 2 8 Ω SE configuration Fig 19 Power dissipation as a function of output power per channel SE configuration VP 35 V fi 1 kHz fosc 345 kHz 1 2 8 Ω SE configuration 2 2 6 Ω SE configuration 3 2 4 Ω SE configuration Fig 20 Efficiency as a function of output power per channel SE configuration Po W 0 120 80 40 20 100 60 001aai705 20 10 30 40 P W 0 25 15 35 5 1 2 3 Po W 0 120 80 40 20 100 60 001aai7...

Page 28: ...N 0 5 8 Ω Fig 21 Output power as a function of supply voltage SE configuration Infinite heat sink used fi 1 kHz fosc 345 kHz 1 THD N 10 8 Ω 2 THD N 0 5 8 Ω 3 THD N 10 16 Ω 4 THD N 0 5 16 Ω Fig 22 Output power as a function of supply voltage BTL configuration Vp V 12 5 40 32 5 30 22 5 25 15 17 5 20 37 5 35 27 5 001aai707 60 20 100 120 140 160 200 40 80 180 Po W 0 1 2 3 4 Vp V 12 5 40 32 5 30 22 5 2...

Page 29: ...onfiguration 3 2 6 Ω SE configuration 4 2 8 Ω SE configuration Fig 23 Closed loop voltage gain as a function of frequency Ripple on VDD short on input pins VP 35 V fosc 345 kHz RL 4 Ω Vripple 2 V p p 1 Mute mode 2 Operating mode 3 Standby mode Fig 24 SVRR as a function of ripple frequency ripple on VDD 001aai709 fi Hz 10 105 104 102 103 30 35 25 40 45 Gv cl dB 20 1 2 3 4 001aai710 fripple Hz 10 10...

Page 30: ...L 4 Ω Vripple 2 V p p 1 Mute mode 2 Operating mode 3 Standby mode Fig 25 SVRR as a function of ripple frequency ripple on VSS VP 35 V fosc 345 kHz 1 Mode voltage down 2 Mode voltage up Fig 26 Output voltage as a function of mode voltage 001aai711 fripple Hz 10 106 104 102 103 100 80 60 40 20 SVRR dB 140 120 3 1 2 VMODE V 0 5 4 2 3 1 4 5 3 5 1 5 2 5 0 5 001aai712 10 4 10 5 10 3 10 2 10 1 10 1 Vo V ...

Page 31: ...heet Rev 02 11 June 2009 31 of 39 NXP Semiconductors TDA8950 2 150 W class D power amplifier VP 35 V fosc 325 kHz Vi 2 V RMS 1 8 Ω 2 6 Ω 3 4 Ω Fig 27 Mute attenuation as a function of frequency 001aai713 fi Hz 10 105 104 102 103 70 80 60 50 αmute dB 90 1 2 3 ...

Page 32: ...ons Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included SOT411 1 98 02 20 02 04 24 0 5 10 mm scale D L L1 L2 E2 E c A4 A5 A2 m L3 E1 Q w M bp 1 d Z e 2 e e 1 23 j DBS23P plastic DIL bent SIL power package 23 leads straight lead length 3 2 mm SOT411 1 v M D x h Eh non concave view B mounting base side B β e1 bp c D 1 E 1 Z 1 d e Dh L L3 m 0 75 0 60 0 55 0 35 30 4 29 9 2...

Page 33: ...original dimensions Notes 1 Limits per individual lead 2 Plastic or metal protrusions of 0 25 mm maximum per side are not included SOT566 3 0 5 10 mm scale HSOP24 plastic heatsink small outline package 24 leads low stand off height SOT566 3 A max detail X A2 3 5 3 2 D2 1 1 0 9 HE 14 5 13 9 Lp 1 1 0 8 Q 1 7 1 5 2 7 2 2 v 0 25 w 0 25 y Z 8 0 θ 0 07 x 0 03 D1 13 0 12 6 E1 6 2 5 8 E2 2 9 2 5 bp c 0 32...

Page 34: ...solder The wave soldering process is suitable for the following Through hole components Leaded or leadless SMDs which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered Packages with solder balls and some leadless packages which have solder lands underneath the body cannot be wave soldered Also leaded SMDs with leads having a pitch smaller than 0 6 mm cannot be...

Page 35: ... It is imperative that the peak temperature is high enough for the solder to make reliable solder joints a solder paste characteristic In addition the peak temperature must be low enough that the packages and or boards are not damaged The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Moisture sensitivity precautions as ...

Page 36: ...older material applied SnPb or Pb free respectively The total contact time of successive solder waves must not exceed 5 seconds The device may be mounted up to the seating plane but the temperature of the plastic body must not exceed the specified maximum storage temperature Tstg max If the printed circuit board has been pre heated forced cooling may be necessary immediately after soldering to kee...

Page 37: ...or manual soldering is suitable 17 Revision history Table 14 Suitability of through hole mount IC packages for dipping and wave soldering Package Soldering method Dipping Wave CPGA HCPGA suitable DBS DIP HDIP RDBS SDIP SIL suitable suitable 1 PMFP 2 not suitable Table 15 Revision history Document ID Release date Data sheet status Change notice Supersedes TDA8950_2 20090611 Product data sheet TDA89...

Page 38: ...uctors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for ...

Page 39: ... inputs 11 9 Limiting values 12 10 Thermal characteristics 12 11 Static characteristics 13 12 Dynamic characteristics 14 12 1 Switching characteristics 14 12 2 Stereo SE configuration characteristics 15 12 3 Mono BTL application characteristics 16 13 Application information 17 13 1 Mono BTL application 17 13 2 Pin MODE 17 13 3 Estimating the output power 17 13 3 1 Single Ended SE 17 13 3 2 Bridge ...

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