Philips TDA8783 Datasheet Download Page 21

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2002 Oct 23

Philips Semiconductors

Product specification

40 Msps, 10-bit analog-to-digital
interface for CCD cameras

TDA8783

APPLICATION INFORMATION

Fig.16 Application diagram.

Depending on the application, the following connections must be made:

(1) The clamp level of the signal input at ADCIN can be tuned from code 00 to code 511 in 0.5 LSB steps of ADC via the serial interface

(clamp ADC activated).

(2) Clamp ADC not activated, direct connection from DACOUT to V

ref

(3) All supply pins must be decoupled with 100 nF capacitors as close as possible to the device.

handbook, full pagewidth

MGM504

TDA8783

OGND

DGND1

CLPOB

AGND4

OFDOUT

AMPOUT

AGND1

VCCA1

CPSDS

AGND5

CLPADC

Vref

IND

INP

CCA3

SHD

SHP

CLPDM

DGND2

CCD2

CCO

AGND3

CLK

AGCOUT

ADCIN

AGND2

CCA2

DEC1

AGND6

SDATA

SEN

STDBY

CCD1

DACOUT

SCLK

from timing

generator

serial

interface

5.0 V

CCD

2.5 to 5.25 V

(3)

(2)

(1)

(3)

5.0 V

(3)

100

2.2

(3)

220

Summary of Contents for TDA8783

Page 1: ...DATA SHEET Product specification Supersedes data of 1999 Jun 25 2002 Oct 23 INTEGRATED CIRCUITS TDA8783 40 Msps 10 bit analog to digital interface for CCD cameras ...

Page 2: ...umption of only 483 mW typ 5 V operation and 2 5 to 5 25 V operation for the digital outputs TTL compatible inputs TTL and CMOS compatible outputs APPLICATIONS CCD camera systems GENERAL DESCRIPTION The TDA8783 is a 10 bit analog to digital interface for CCD cameras The device includes a correlated double sampling circuit AGC and a low power 10 bit Analog to Digital Converter ADC together with its...

Page 3: ...ICCA analog supply current 78 95 mA ICCD digital supply current 18 20 mA ICCO digital outputs supply current fCLK 27 MHz CL 20 pF ramp input 1 mA ADCres ADC resolution 10 bits Vi CDS p p CDS input voltage peak to peak value 400 1200 mV GCDS CDS output amplifier gain 6 dB fCLK max maximum clock frequency fcut CDS 120 MHz fcut AGC 54 MHz 40 MHz AGCdyn AGC dynamic range 30 dB Ntot rms total noise fro...

Page 4: ...C CLOCK GENERATOR 10 BIT ADC REGULATOR SERIAL INTERFACE 4 BIT DAC CUT OFF OUTPUTS BUFFER 5 4 2 7 6 9 10 14 11 12 13 15 16 17 18 20 21 22 23 19 24 36 3 25 26 27 28 29 30 31 32 33 34 35 37 38 39 40 41 42 43 44 45 48 46 47 IND INP AGND3 SHD SHP CLPDM CLK DGND2 VCCO VCCD2 VCCA3 OE D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DGND1 OFDOUT OGND VCCD1 STDBY SEN AGND6 SCLK SDATA DEC1 VRT VRB VCCA2 DACOUT Vref CLPADC AGN...

Page 5: ... 2 VRB 16 ADC reference voltage BOTTOM code 0 VRT 17 ADC reference voltage TOP code 1023 DEC1 18 decoupling 1 decoupled to ground via a capacitor AGND6 19 analog ground 6 SDATA 20 serial data input for the 4 control DACs 9 bit DAC for AGC gain 8 bit DAC for frequency cut off additional 8 bit DAC for OFD output voltage 10 bit DAC for ADC clamp level and the standby mode per block and edge pulse con...

Page 6: ...se input SHD 44 data sample and hold pulse input VCCA3 45 analog supply voltage 3 INP 46 pre set input signal from CCD IND 47 data input signal from CCD AGND3 48 analog ground 3 SYMBOL PIN DESCRIPTION Fig 2 Pin configuration 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 12 24 37 25 TDA8783HL MGM492 OGND D9 D8 D7 D5 D4 D3 ...

Page 7: ...opriate to handling integrated circuits THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT VCCA analog supply voltage note 1 0 3 7 0 V VCCD digital supply voltage note 1 0 3 7 0 V VCCO output stages supply voltage note 1 0 3 7 0 V VCC supply voltage difference between VCCA and VCCD 1 0 1 0 V between VCCA and VCCO 1 0 4 0 V between VCCD and VCCO 1 0 4 0 V Vi input voltage referenced t...

Page 8: ...level input current VCLK 0 8 V 1 1 µA IIH HIGH level input current VCLK 2 0 V 20 µA Zi input impedance fCLK 27 MHz 46 kΩ Ci input capacitance fCLK 27 MHz 1 pF INPUTS SHP AND SHD VIL LOW level input voltage 0 0 8 V VIH HIGH level input voltage 2 0 VCCD V IIL LOW level input current VIL 0 8 V 6 µA IIH HIGH level input current VIH 2 0 V 0 µA INPUTS SEN SCLK SDATA OE STDBY CLPDM CLPOB AND CLPADC VIL L...

Page 9: ...300 Ω VAMPOUT p p output amplifier dynamic voltage peak to peak value 2 4 V VAMPOUT bl output amplifier black level voltage 1 5 V VAGCOUT p p AGC output amplifier dynamic voltage level peak to peak value 2000 mV VAGCOUT bl AGC output amplifier black level voltage Vref connected to DACOUT Vref V ZAGCOUT AGC output amplifier output impedance at 10 kHz 5 Ω IAGCOUT AGC output static drive current stat...

Page 10: ...ramp input 0 6 1 5 LSB DNL differential non linearity ramp input 0 2 0 75 LSB td s sampling delay time 5 ns Total chain characteristics CDS AGC ADC td delay between SHD and CLK 50 at rising edges CLK and SHD transition full scale code 0 to 1023 fcut CDS 120 MHz fcut AGC 54 MHz Vi CDS 600 mV 30 ns Ntot rms total output noise RMS value fcut CDS 120 MHz fcut AGC 40 MHz note 2 GAGC 4 5 dB 0 125 LSB GA...

Page 11: ...ignal input 3 Depending on operating pixel frequency the output voltage and capacitance must be determined according to the output delay timings to d see Fig 5 ZOFDOUT additional 8 bit control DAC OFD output impedance 2000 Ω IOFDOUT OFD output current drive static 50 µA ADC clamp control DAC see Fig 8 VDACOUT p p ADC clamp 10 bit control DAC output voltage peak to peak value 1 V VDACOUT DC output ...

Page 12: ...ATCH SELECTION D0 LSB MSB SDATA SCLK SEN 8 bit DAC 10 bit DAC MGM515 AGC control frequency control CDS and AGC standby control or edge clocks D1 D2 D3 D4 D5 10 D6 SHIFT REGISTER D7 D8 D9 A0 A1 A2 8 D7 to D0 9 D8 to D0 8 D7 to D0 7 D6 to D0 10 D9 to D0 Fig 4 Loading sequence of control DACs input data via the serial interface handbook full pagewidth MGE373 A2 SDATA SCLK SEN A1 A0 D9 D7 D6 D5 D4 D3 ...

Page 13: ...S D4 to D7 are used for AGC D8 and D9 should be set to logic 0 0 1 0 AGC gain control D8 to D0 0 1 1 Partial standby controls for power consumption optimization Only the 4 LSBs D3 to D0 are used Edge control for pulses SHP SHD CLAMP and clock ADC D0 1 CDS AGC in standby ICCA ICCD 35 mA D1 1 OFD DAC in standby ICCA ICCD 95 mA D2 1 6 dB amplifier output on AMPOUT pin in standby ICCA ICCD 95 5 mA D3 ...

Page 14: ...0 Msps 10 bit analog to digital interface for CCD cameras TDA8783 handbook full pagewidth MGR395 N IND SHP 1 4 V SHD CLK ADCIN DATA N 3 N 2 N 1 N 1 N N tCDS tCPH td s td to d to h tn IN SHP tn IN SHD 90 10 1 4 V 1 4 V N 3 N 2 Fig 5 Pixel frequency timing diagram ...

Page 15: ...CD cameras TDA8783 Fig 6 Line frequency timing diagram 1 When dummy pixels are not available handbook full pagewidth MGR396 CLPADC active HIGH CLPDM active HIGH CLPOB active HIGH OPTICAL BLACK HORIZONTAL FLYBLACK DUMMY VIDEO VIDEO AGCOUT CLPDM CLPADC WINDOW CLPOB WINDOW 1 1 1 pixel CLPDM CLPADC WINDOW 1 pixel ...

Page 16: ...as a function of DAC input code handbook halfpage MGM507 GAGC dB 34 5 4 5 0 319 511 AGC control DAC input code Fig 8 DAC voltage output as a function of DAC input code handbook full pagewidth 0 ADC CLAMP DAC voltage output V 2 5 1 5 1023 ADC CLAMP control DAC input code MGM508 0 OFD DAC voltage output V 3 7 2 3 255 OFD control DAC input code ...

Page 17: ...meras TDA8783 Fig 9 Typical clamp current for pin CPCDS handbook halfpage MGR397 100 0 100 I µA V V 200 mV 2 00 Fig 10 Typical clamp current for pins IND and INP handbook halfpage MGR398 300 0 300 I µA V V 400 mV 2 85 Fig 11 Typical clamp current for pin Vref handbook halfpage MGR399 200 0 200 I µA V V 400 mV Vref ...

Page 18: ...ace for CCD cameras TDA8783 Fig 12 CDS settling time and bandwidth 1 fcut 2 tset 10 bits accuracy 3 tset 9 bits accuracy 4 tset 8 bits accuracy handbook full pagewidth 160 120 40 0 80 MGR441 F 0 5 A 1 6 B 2 7 C 3 8 D 4 9 E 4 bit control DAC input code fcut MHz 300 250 50 0 150 100 200 tset ns 2 4 1 3 ...

Page 19: ... handbook full pagewidth F 60 40 20 0 0 5 A 1 6 B 2 7 C 3 8 D 4 9 E MGR401 4 bit control DAC input code fcut MHz Fig 14 CDS output handbook full pagewidth 1 6 1 6 1 2 0 4 0 0 0 4 1 2 0 8 0 8 0 2 0 6 1 4 1 0 MGR442 Vi CDS p p V Vo CDS p p V 2 3 4 6 5 1 1 tset CDS 12 ns 2 tset CDS 10 ns 3 tset CDS 8 ns 4 tset CDS 7 ns 5 tset CDS 6 ns 6 tset CDS 5 ns ...

Page 20: ...x 18 MHz control DAC 10H fcut CDS 120 MHz fcut AGC 40 MHz 3 fpix 10 MHz control DAC 31H fcut CDS 80 MHz fcut AGC 30 MHz 4 fpix 5 MHz control DAC 43H fcut CDS 35 MHz fcut AGC 12 MHz 5 fpix 1 MHz control DAC F8H fcut CDS 6 MHz fcut AGC 4 MHz 6 fpix 375 kHz control DAC FFH fcut CDS 4 MHz fcut AGC 4 MHz handbook full pagewidth 13F code 3 2 1 0 00 40 80 C0 100 34 5 4 5 10 5 16 5 22 5 28 5 MGR443 GAGC d...

Page 21: ...ref 3 All supply pins must be decoupled with 100 nF capacitors as close as possible to the device handbook full pagewidth MGM504 1 2 3 4 5 6 7 8 9 10 11 36 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 35 34 33 32 31 30 29 28 27 26 12 25 TDA8783 OGND D9 D8 D7 D5 D4 D3 D2 D1 D0 DGND1 CLPOB AGND4 OFDOUT AMPOUT AGND1 VCCA1 CPSDS AGND5 CLPADC Vref D6 IND INP V CCA3 SHD SHP CL...

Page 22: ...s are necessary on all supply pins as shown in Fig 16 Separate analog and digital supplies provide the best performance If it is not possible to do this on the board then decouple the analog supply pins effectively from the digital supply pins The decoupling capacitors must be placed as close as possible to the IC package In a two ground system in order to minimize the noise from package and die p...

Page 23: ...7 0 18 0 12 7 1 6 9 0 5 9 15 8 85 0 95 0 55 7 0 o o 0 12 0 1 0 2 1 0 DIMENSIONS mm are the original dimensions Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included 0 75 0 45 SOT313 2 MS 026 136E05 99 12 27 00 01 19 D 1 1 1 7 1 6 9 HD 9 15 8 85 E Z 0 95 0 55 D bp e E B 12 D H bp E H v M B D ZD A ZE e v M A 1 48 37 36 25 24 13 θ A1 A Lp detail X L A 3 A2 X y c w M w M 0 2...

Page 24: ...ng and non wetting can present major problems To overcome these problems the double wave soldering method was specifically developed If wave soldering is used the following conditions must be observed for optimal results Use a double wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave For packages with leads on two sides and a pitch e large...

Page 25: ...eatsink on the bottom side the solder cannot penetrate between the printed circuit board and the heatsink On versions with the heatsink on the top side the solder might be deposited on the heatsink surface 4 If wave soldering is considered then the package must be placed at a 45 angle to the solder wave direction The package footprint must incorporate solder thieves downstream and at the side corn...

Page 26: ...values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting va...

Page 27: ...2002 Oct 23 27 Philips Semiconductors Product specification 40 Msps 10 bit analog to digital interface for CCD cameras TDA8783 NOTES ...

Page 28: ...bility will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Philips Semiconductors a worldwide company Contact information For additional information please visit http www semiconductors philips com Fax 31 40 27 24825 For sales offices addresses send e mail to sale...

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