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Philips TDA5360, Datasheet

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Philips TDA5360 Datasheet Download Page 12

1998 July 30

Philips Semiconductors

Objective Specification, Revision 2.2

Pre-Amplifier for Hard Disk Drive with 
MR-Read / Inductive Write Heads

TDA5360

12

10 BIASING OF THE MR ELEMENT

This preamplifier has been designed for SAL and GMR elements. Programming bit GMR in Reg. 01 select either a SAL 
range (LOW) or a GMR range (HIGH).
By programming bit PORI in Reg. 01, the user can program either a constant current bias (LOW) or a constant power 
bias (HIGH) for the MR element. The value of the current/power is programmed on 5 bits via Reg. 02.

If bit PORI in Reg. 01 is HIGH, a constant power bias is maintained accross the MR element.

The power is defined as :

Pw = R

MR

 * I

MR 

2

, where Pw is constant over temperature and process.

In power bias mode, two power ranges are possible :

For SAL heads

1.5mW to 9.25 mW 

in steps of 0.25mW

For GMR heads

375uW to 2.3 mW

in steps of 0.0625mW

Note : 

whatever Power programmation is used, the I

MR

 current flowing into the MR element will be within the min-

max range given below. 

If bit PORI in Reg.01 is LOW, then the biasing scheme shall revert to constant current instead of constant power. 
I

MR

 is then constant over temperature and process.

In current bias mode, two current ranges are possible :

For SAL heads :

4 to 10.2 mA in steps of 0.2 mA

For GMR heads :

3 to 6.1 mA  in steps of 0.1 mA

Note : 

In GMR mode,  IMR current is guaranted up to 5.1mA

6.1mA can be reached under certain supplies/Rmr conditions.

10.1

MR Head Resistance and Temperature Measurement 

By programming RANGE0,RANGE1 bits in Reg. 08, the user can select either a Rmr measurement or a Temperature 
measurement (junction temperature).

Setting DIGON bit HIGH launch a digitazation
The settling time of the digitization operation is less than 

TBD 

µ

s. 

A 5 bit code is then available in Reg. 08, as long as DIGON stays HIGH, 
Setting DIGON bit LOW, reset the 5 bit code.

In case of Rmr measurement, the user have access to two Rmr range by programming RANGE0 and RANGE1 bits.

In case of Temperature too high condition (T > 140

o

C), during a Temperature measurement, a Fault is triggered on FLT 

line and a error code is available in Reg. 07.

Summary of Contents for TDA5360

Page 1: ... TDA5360 Pre Amplifier for Hard Disk Drive with MR Read Inductive Write Heads Objective specification Revision 2 2 1998 Jul 30 INTEGRATED CIRCUITS ...

Page 2: ...CTIVE WRITE MODE 9 3 ACTIVE STW MODE 9 4 STANDBY MODE 9 5 SLEEP MODE 10 BIASING OFTHE MR ELEMENT 10 1 MR HEAD RESISTANCE AND TEMPERATURE MEASUREMENT 10 2 FAULT MODE 10 3 SERIAL INTERFACE ADDRESSING 10 4 SERIAL INTERFACE REGISTER BIT ALLOCATION 10 5 SERIAL INTERFACE OPERATIONS 10 6 REGISTERS DESCRIPTION 11 SERIAL INTERFACE TIMING 12 ELECTRICAL PARAMETERS 12 1 DC CHARACTERISTICS 12 2 READ CHARACTERI...

Page 3: ...t Programmable voltage current mode write data input Programmable voltage current mode read data output Programmable Read gain Programmable Reader input impedance Thermal asperity detection with programmable threshold Thermal asperity compression with extensive programmability High spurious noise rejections Internal Dummy Head available for MR heads protection during switchings FAST mode available...

Page 4: ... Rmr 66Ω GAIN0 0 GAIN1 1 50 dB fHR 3dB frequency bandwidth Rmr 66Ω Lmr 30 nH 3dB without Boost SAL GMR 225 225 MHz MHz CMR Common Mode Rejection Imr 8 mA Rmr 66Ω 10MHz f 200MHz 1 MHz f 10 MHz f 100 kHz 1mV input signal 20 40 60 dB dB dB PSR Power Supply Rejection 200mVpp on Vcc or Vee Imr 8mA Rmr 66Ω 10MHz f 200MHz 1 MHz f 10 MHz f 100 kHz 20 40 60 dB dB dB tr tf Write Current Rise Fall times 0 8 ...

Page 5: ...can be enhanced by using programmable high frequency gain boost Fast settling features are used to keep the transients short As an option the Read amplifier may be left biased during writing so as to reduce the duration of these transients even further The Write amplifier has a programmable current overshoot which may be added to the programmable steady state write current Fault protection is prov...

Page 6: ...IAS POWER SETTING WRITE BANDGAP THERMAL ASPERITY DETECTOR RDp RDn FLT Rext WDp WDn SDATA SCLK SEN CURRENT RFE hybrid sense RMR TA handling Rin 2bits voltage pre driver boost 1 bit boost 2bits WDI V I Interface 1 bit voltage driven pre driver boost 1bit CODING Av 1 5 bit On Off TA CORRECTOR 3bits DIGITIZER Rmr measure temperatue WDI Read Back End RFE hybrid sense RMR Rin 2bits V I out CURRENT 4 bit...

Page 7: ...NGEMENT Fig 2 TDA5360 pad arrangement pads up WN11 WP11 RP11 RN11 RN10 RP10 WP10 WN10 WN9 WP9 RP9 RN9 RN8 RP8 WP8 WN8 VEE WN4 WN5 WN6 WP5 RP5 RN5 RN4 RP4 WP4 VCC WN7 WP7 RP7 RN7 RN6 RP6 WP6 WP2 RP2 RN2 RN3 RP3 WP3 WN3 VEE WN2 WP0 RP0 RN0 RN1 RP1 WP1 WN1 WN0 VCC VCC VCC VCC GND GND STWN CS1 CS0 REXT DRN BFAST SDATA SCLK SEN FLT WDP WDN RWN RDN RDP SHIELDP SHIELDN ...

Page 8: ...input in MDS mode REXT a 10kΩ external resistor must be connected between REXT and GND SEN logic input Serial Enable line Active High SCLK logic input Serial Clock line 40 MHz max SDATA logic input output Serial Data line Bi directional interface BFAST logic input Controls reader passband or enables the Imr generator depending on the state of BFCTL bit from Reg 01 DRN logic input Selects the dummy...

Page 9: ...puts RDP and RDN are in phase with the MRP and MRN head ports The read data at pins RDP RDN can output either voltage or current depending on how the RVORI bit in Reg 01 is set LOW or HIGH respectively The polarity convention for current mode is positive pin with least current flowing negative pin with most current flowing Write current is not present in read mode under any circumstances either tr...

Page 10: ...between the REXT pin and GND The reference voltage on REXT pin is stable over the entire operating temperature range and process Internal compensation networks are optimized and provided to control the write current shape and settling characteristics based on specified head loads The value can be programmed in Reg 04 9 3 Active STW mode In Active Read or Active Write mode only one head in one prea...

Page 11: ...Dynamic current consumption during operation of the Serial Interface in the Sleep mode and owing to external activity at the inputs to the Serial Interface is not included In all Modes including the Sleep mode data registers can be programmed Sleep is the default Mode at power up Switching to other modes takes less than 0 1 ms The CMM of RDP and RDN is the same as in Standby or Active mode see Not...

Page 12: ...nt will be within the min max range given below If bit PORI in Reg 01 is LOW then the biasing scheme shall revert to constant current instead of constant power IMR is then constant over temperature and process In current bias mode two current ranges are possible For SAL heads 4 to 10 2 mA in steps of 0 2 mA For GMR heads 3 to 6 1 mA in steps of 0 1 mA Note In GMR mode IMR current is guaranted up t...

Page 13: ...output is an open collector to an external resistor of 5Kohms connected to 5V Table 1 Fault Conditions Mode Fault condition FCOD3 FCOD2 FCOD1 FCOD0 Both No fault 0 0 0 0 Read Write current present 0 0 0 1 Fault code not used 0 0 1 0 Thermal Asperity detected 0 0 1 1 Read head open 0 1 0 0 Write No write current 0 1 0 1 Write Data frequency to low 0 1 1 0 Write head open 0 1 1 1 Write head shorted ...

Page 14: ...which set FLT HIGH An action can eventually be taken FAULT ACTION No write current in write mode Disable write current Rext pin open or shorted to GND or Vcc Disable write current Open write head or shorted to GND Do not disable write current Write data frequency too low Do not disable write current Power supplies too low Disable write current lllegal head address i e HD 12 13 14 15 Disable write ...

Page 15: ... 1 0 CS1 CS0 RWN 7 X 0 1 1 1 CS1 CS0 RWN 8 X 1 0 0 0 CS1 CS0 RWN 9 X 1 0 0 1 CS1 CS0 RWN 10 X 1 0 1 0 CS1 CS0 RWN 11 X 1 0 1 1 CS1 CS0 RWN Register D7 D6 D5 D4 D3 D2 D1 D0 0 HS3 HS2 HS1 HS0 SELT SELF LCS1 LCS0 1 X PORI GMR RIN1 RIN0 RVORI WVORI BFCTL 2 DUMMY PWR4 PWR3 PWR2 PWR1 PWR0 GAIN1 GAIN0 3 HFZ3 HFZ2 HFZ1 HFZ0 X X LFP1 LFP0 4 IW4 IW3 IW2 IW1 IW0 WCP2 WCP1 WCP0 5 TRANGE TAD TAC TAD4 TAD3 TAD2...

Page 16: ...an start The data read back can be either 3 3V compatible or 5V compatible depending on SIOLV bit in Reg 09 10 5 2 PROGRAMMING DATA During a programming sequence the last eight bits d0 d7 before SEN goes LOW are shifted into an input register When SEN goes LOW the communication sequence is ended and the data in the input register are copied in parallel to the data register corresponding to the dec...

Page 17: ...t or power LOW SAL range HIGH GMR range RIN1 0 define the input impedance of the reader 0 0 30Ω 0 1 23Ω 1 0 18Ω 1 1 15Ω RVORI Reader output buffer mode LOW Voltage mode HIGH Current mode WVORI Writer data inputs mode LOW Voltage mode HIGH Current mode Note 1a BFCTL Control of BFAST pin functionality Note 1b 2 Reader Bias Register DUMMY Dummy head is selected in read mode if LOW PWR4 PWR0 define Im...

Page 18: ...A detection circuits are enabled TAC if HIGH the TA Compression circuits are enabled TAD4 TAD0 5 bits for TAD threshold programmation referred to the input Vth mV 0 390 3 170 TRANGE 0 177 TAD0 2 TAD1 4 TAD2 8 TAD3 16 TAD4 Note 5 6 Vendor Register VEND7 VEND0 8 bits for identification read back only bits 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 1 rev1 0 1 0 0 0 0 1 1 rev2 7 Fault Management Register FLT2 FLT0...

Page 19: ...M4 DIGON is set HIGH to launch a digitazation Note 8 9 Operating mode Register SIOLVL level of SDATA when reading back a register if LOW 3 3V compatible if HIGH 5 0V compatible RSTDMY define functionality of DRN pin Note 9a MODE1 MODE0 2 power management control bits 0 0 Sleep Mode 0 1 Standby Mode 1 0 Active Mode or STW one head 1 1 Test Mode or STW two heads Note 9b 11 Thermal Asperity Compressi...

Page 20: ... Note 3 For differentiator only GAIN0 GAIN1 1 the midrange setting HFZ3 1 HFZ0 HFZ1 HFZ2 0 have a gain of 44dB at 100 Mhz i e gain 100 Mhz 80 10 HFZ0 2 HFZ1 4 HFZ2 8 HFZ3 For gain plus differentiator other GAIN0 GAIN1 programmation the midrange setting HFZ3 1 HFZ0 1 2 0 create a zero at 300 Mhz independent of the gain bits HF Zero f 2400 MHz HFZ0 2 HFZ1 4 HFZ2 8 HFZ3 i e gain 150 75 GAIN0 2 GAIN1 ...

Page 21: ... 07 See Section 10 2 for details The FAULT pin is flagged as long as the error remains present When the error condition is removed the FAULT pin toggles to a non error state but the 4 bits code still remains present in Reg 07 To Reset the FAULT code the user should reprogramm Reg 09 Some fault detections can be inhibited via FLT2 1 0 bits If an action is linked to the inhibited detection for examp...

Page 22: ...at case Head Hx and Head H x 6 will be selected in STW Servo Track Write 2 heads Note 11a ENFST define BFAST pin functionality when Thermal Asperity Compression is ON Note 11b Thermal Asperity Compression TAC functionality When a thermal asperity occurs at the reader input the reader output signal get superposed with an amplified signal corresponding to a certain extent to the thermal asperity RST...

Page 23: ...60 23 The aim of the TAC is to limit the amplitude and the duration of the perturbation seen at the reader output Because thermal asperity amplitude is not constant the TAC need some threshold programmation to define the sharpness of the response note that reducing the TAC threshold also impact the Low corner frequency value of the read amplifier ...

Page 24: ...MING 0 Reg 00H SEN SCLK SDATA a0 0 a2 a1 a3 a4 a5 a6 a7 Address Data 1 Tclk 0 5 Tclk d0 d1 d2 d3 d4 d5 d5 d7 SEN SCLK SDATA a0 1 a2 a1 a3 a4 a5 a6 a7 Address Data 2 Tclk 1 5 Tclk d0 d1 d2 d3 d4 d5 d6 d7 READ WRITE t 5ns t 5ns When Fclk 20 MHz and a register reading is performed it is necessary to extend the clock period as above When Fclk 20 MHz this is not necessary 1 Tclk ...

Page 25: ...of SCLK 5 ns tf_sclk_sen last SCLK to 90 of SEN 5 ns tr tf rise fall time 10 90 2 Tclk 4 ns t_sen_sen delay between 2 SEN 75 ns SCLK timing frequency 40 MHz tr tf rise fall time 10 90 2 Tclk 4 ns tclklow 10 of SEN to CLK state change 5 ns tclkwidth TBD ns SDATA timing tsetup data setup time before 10 of SCLK 5 Tclk 2 ns thold data hold time after 90 of SCLK 5 Tclk 2 ns tsetup thold tr tclkperiod t...

Page 26: ... 8mA 20 12 8 mA Write Mode IWR 30 8 mA 150 80 60 mA Standby Mode 200 5 0 uA Sleep Mode 200 5 0 uA Power Dissipation Read Mode I MR 8mA 365 435 525 mW Pw TJ 105 C Write Mode IWR 30 8 mA 800 1050 1625 mW VIL Input Low Voltage TTL 0 0 8 V V IH Input High Voltage TTL 2 4 5 V IIL Input Low Current VIL 0 8 V PECL TTL 160 50 uA uA IIH Input High Current VIH 2 4V PECL TTL 50 80 uA uA VOL Output Low voltag...

Page 27: ... 375 4 2 1 9 25 2 30 mW mW MR Power Tolerance 3 I MR 10mA 5 5 MR Bias Current Overshoot 0 RMR Digitizer Accuracy 5 VRext Rext Reference Voltage 1 31 V AVd Differential Voltage Gain VIN 1mVPP 20MHz R Load dif 330 Ohm I MR 8mA RMR 66 Ohm RIN 18 Ohm GAIN0 0 GAIN1 1 GMR 0 48 50 52 dB fHR Passband Upper 3dB Frequency RMR 66Ω LMR 30nH 3dB Without boost 225 MHz f LR Passband Lower 3dB Frequency R MR 66Ω ...

Page 28: ...CC or VEE IMR 8mA RMR 66Ω 10 Mhz f 200 Mhz 1 Mhz f 10 Mhz f 100 KHz GMR 0 20 40 60 dB CS Channel Separation Unselected Channels V IN 1mV PP 1 f 200 MHz 50 dB VOS Output Offset Voltage IMR 8mA RMR 66Ω GAIN0 GAIN1 0 GMR 0 100 mV VOCM Common Mode Output Voltage 2 45 V RSEO Single Ended Output Resistance 17 5 Ohm I O Output Current AC Coupled Load RDP to RDN RVORI HIGH RVORI LOW TBD 4 mA MR head poten...

Page 29: ... IWR Write Current Tolerance 7 7 Differential Head Voltage Swing Iwr 50mA TBD 16 V PP IUH Unselected Head Current Glitch I W 50mA 1 mA PK fDATA Write Data Frequency for Safe Condition FLT Low 1 MHz RO Differential Output Resistance 30 60 Ohm CO Differential Output Capacitance 6 pF A SYM Asymmetry A SYM tr tf Write Data has 50 duty cycle 0 5ns rise fall time load short 0 1 ns t r t f Rise Fall Time...

Page 30: ...noise voltage excluding the noise of the MR resistor iis defined as follows PARAMETER CONDITIONS MIN TYP MAX UNIT SI Serial Interface timing Note 6 t RW R WN to Write Mode To 90 of write current 50 ns SEN to Write Mode To 90 of write current 50 ns t WR R WN to Read Mode Reader outputs loaded with high pass single ended filters R 165Ω C 270pF Writer output shorted Note 7 175 ns tCS CS to Read Mode ...

Page 31: ...ction 11 for Serial Interface timing diagrams 7 This tWR is defined for a specific load on RDP RDN reader outputs tWR is the time between R Wn going HIGH and the time when 90 of the signal envelop is present at RDPch RDNch AND the differential DC decaying at RDPch RDNch is below 10mV Changing the load of the preamp will change tWR according to the new RC time constant 8 When changing MR bias curre...

Page 32: ...ge Low level PECL input voltage 0 4 2 4 0 7 3 2 2 8 1 5 VCC V V V Imode Writer input Differential Peak to Peak input current High level input current Low level input current 0 4 1 4 0 8 1 2 0 4 1 0 0 1 mA mA mA Tamb Ambient temperature 0 55 70 C Tj Junction temperature when reading when writing 70 110 130 C RMR MR element resistance 46 66 86 Ohm Ll tot Total lead inductance to the head in each lea...

Page 33: ...ze the PSRR 14 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER MIN MAX UNIT VCC Positive supply voltage 0 5 6 0 V VEE Negative supply voltage 6 0 0 5 V VIN Digital input voltage 0 5 VCC 0 3V V Vn1 Voltage on all pins except VCC read inputs RPx RNx write outputs WPx WNx x 0 to 11 and the ones mentionned in this table but not higher than 0 5 5 5 VCC 0 5 V V Vn2 Voltage on write driver outputs WPx WNx but ...

Page 34: ...pplication Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyrigh...

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