Circuit Descriptions, List of Abbreviations, and IC Data Sheets
EN 50
SD-5.31SL
9.
•
Miscellaneous
Figure 9-5 Block diagram back-end
DVD Back-end Host Processor
The SD5.31 is designed for the LSI-Logic ZiVA-5 family.
Figure 9-6 ZiVA-5 Block Diagram
Some of the DVD related features of this IC are:
•
Video decoder supports MPEG1 and MPEG2
•
Audio decoder supports AC-3, MPEG1, MPEG2, DTS,
PCM, S/PDIF, and MP3.
•
PAL/NTSC video encoder with simultaneously Y/C, CVBS
and RGB/YUV outputs
•
The video encoder supports Closed Caption and allows
MacroVision 7.0/6.1
•
Full screen On Screen Display (OSD) generator
•
On-chip PLLs to generate all necessary clocks (as
reference a 13.5 MHz xtal is used).
CPU
The ZiVA-5 incorporates a 32-bit SPARC host CPU for audio
processing and special features. The SPARC CPU is designed
to act as the system host processor (thus removing the
requirement for an external host CPU with associated
memory).
GPIO
(misc)
GPIO
I2C
Master
MSCL
MSDA
I2C
INT
LSI Logic
ZiVA 5+
Clock
circuit
Reset
Circuit
SYSRSTn
E-LINK
ATAPI
I2S
KOK
A-D
Microphone
input
SDRAM interface
Host interface
Two SDRAM configuration option
2x TSOP54 SDRAM
2pcs x 1M x 16 x 4 = 128 Mbits
MUX
Audio I2S Input
XCLK
BCLK
LRCLK
Ext I2S input
Digital
audio
SPDIF
input
SPDIF - I2S
conv.
Module interface bus
MA[0:11]
BA[0:1]
MD[0:31]
MCS0n
MRASn
MCASn
MWEn
MCLK
MDQM[0:3]
MCS1n
UPA[1:3]
UPD[0:15]
HDTACKn
LDS
UDS
HDMACK
HDMARQ
ATAPIINTn
IDECS0n
IDECS1n
ATAPIRSTn
UPA[1:3]
UPD[0:15]
ALE
SYSRSTn
HDTACKn
MEDUSAINTn
UDS
LDS
RWn
MEDUSACSn
ATAPI connector
ZK5 E-LINK
connector
Flash/
ROM
2M Bytes
TSOP48
1M x 16 M29W160
(*byte swapped)
UPA[1:22]
UPD[0:15]
SYSRSTn
UDS
FLASHCSn
Transparent Latch
74LVC573
74LVC573
74LVC573
UPA[1:3]
UPD[0:15]
ALE
MSCL
MSDA
DAC
(2/6 Ch)
64 kbits
NV RAM
Analog Audio Out
I2C
Slave
SCL
SDA
Analog
video
VDAC[0:4]
Digital
audio
SPDIF
Audio I2S output
Service and JTAG bus
Digital
video
VDATA(0:7)
ITUT -656
Digital
TDO
TDI
TMS
TCK
Digagnostic port
RST1
RXD1
TXD1
CTS1
XCLK
BCLK
LRCLCK
ADATA[0:3]
GND
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
NC
GND
GND
GND
NC
GND
NC
NC
DA2
CS1n
GND
RESET
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
GND
DMARQ
DIOWn
DIORn
IORDYn
DMACK
INTRQ
DA1
DA0
CS0n
NC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
ATAPI connector
+5V
+5V
SYSRSTn
UPA3
UPA1
UPD14
UPD12
UPD10
GND
UPD7
UPD5
UPD3
UPD1
DTACKn
UDS
GNG
GND
MEDUSACSn
ALE
UPA2
UPA15
UPA13
UPA11
UPA9
UPD8
UPD6
UPD4
UPD2
UPD0
MEDUSAIONTn
LDS
RWn
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
ZK5 E-LINK connector
CL 36532043_010.eps
190503
13.5 MHz Crystal
Bus Interface Unit
32-bit SPARC
Microprocessor
+Audio DSP
Phase
Lock
Loop
IDC
SDRAM Controller
Audio
Output
Unit
JTAG
DVD Drive
Parallel/Serial
IDS Stereo In
IEC958/1937
Digital Video
LPCM 8-ch
Audio Out
ZiVA
A/V Core
Audio
Input Unit
Decryption
Track Buffer
Processor
NTSC/PAL/480P
Video Encoder
with
TrueScan
De-Interfacer
Composite
Y/R
Cr/Pr/G
Cb/Pb/B
C
Five 10-bit
Video
DACs
CCIR 656
ASYNC BUS
SDRAM (64/128Mbits)
UARTs
IR
EIDE
GPIO
SPI
Multi-Plane
2D
Graphics
Engine
Interface
CL36532043_013.eps
150503