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Philips Semiconductors

Product data sheet

SCC2691

Universal asynchronous receiver/transmitter (UART)

2006 Aug 04

17

tTXD

tTCS

1 BIT TIME

(1 OR 16 CLOCKS)

TxD

TxC

(INPUT)

TxC

(1X OUTPUT)

SD00092

Figure 8. Transmit Timing

tRXS

tRXH

RxC

(1X INPUT)

RxD

SD00093

Figure 9. Receive Timing

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Summary of Contents for SCC2691

Page 1: ... SCC2691 Universal asynchronous receiver transmitter UART Product data sheet Supersedes data of 1998 Sep 04 2006 Aug 04 INTEGRATED CIRCUITS ...

Page 2: ...of several magnitudes The UART is fully TTL compatible and operates from a single 5V power supply FEATURES Full duplex asynchronous receiver transmitter Quadruple buffered receiver data register Programmable data format 5 to 8 data bits plus parity Odd even no parity or force parity 1 1 5 or 2 stop bits programmable in 1 16 bit increments 16 bit programmable Counter Timer Baud rate for the receive...

Page 3: ...n Plastic Small Outline Large SOL Package SCC2691AC1D24 SOT137 1 BLOCK DIAGRAM 8 D0 D7 RDN WRN CEN A0 A2 RESET INTRN X1 CLK X2 TIMING CONTROL INTERNAL DATA BUS 3 BUS BUFFER OPERATION CONTROL ADDRESS DECODE R W CONTROL INTERRUPT CONTROL IMR ISR TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER TIMER CRYSTAL OSCILLATOR POWER DOWN LOGIC CSR ACR CTUR CTLR CHANNEL A TRANSMIT HOLDING REG TRANSMIT SHIFT...

Page 4: ... resistor X1 CLK 9 12 I Crystal 1 Crystal connection or an external clock input A crystal of a clock the appropriate frequency nominally 3 6864 MHz must be supplied at all times For crystal connections see Figure 7 Clock Timing X2 10 13 I Crystal 2 Crystal connection See Figure 7 If a crystal is not used it is best to keep this pin not connected although it is permissible to ground it RxD 2 3 I Re...

Page 5: ...ER TEST CONDITIONS Min Typ Max UNIT VIL VIH Input low voltage Input high voltage 0 8 V All except X1 CLK X1 CLK 2 0 8VCC VCC V V VOL VOH 4 Output low voltage Output high voltage except open drain outputs IOL 2 4mA IOH 400µA 2 4 0 4 V V IIL Input leakage current VIN 0 to VCC 10 10 µA ILL Data bus 3 State leakage current VO 0 4 to VCC 10 10 µA IOD Open drain output leakage current VO 0 4 to VCC 10 1...

Page 6: ...nput on IP pin 350 ns tTCS Output delay from TxC low at OP pin to TxD data output 0 150 ns Receiver timing Figure 9 tRXS RxD data setup time before RxC high at external clock input on IP pin 100 ns tRXH RxD data hold time after RxC high at external clock input on IP pin 100 ns NOTES 1 Parameters are valid over specified temp range See Ordering Information table for applicable operating temp and VC...

Page 7: ...ck consists of a crystal oscillator a baud rate generator a programmable 16 bit counter timer and two clock selectors The crystal oscillator operates directly from a 3 6864MHz crystal connected across the X1 CLK and X2 inputs with a minimum of external components If an external clock of the appropriate frequency is available it may be connected to X1 CLK If an external clock is used instead of a c...

Page 8: ...op bit is detected the receiver will immediately look for the next start bit However if a non zero character was received without a stop bit i e framing error and RxD remains low for one half of the bit period after the stop bit was sampled then the receiver operates as if a new start bit transition had been detected at that point one half bit time after the stop bit was sampled The parity error f...

Page 9: ...ime refers to the condition where the change of state is just missed and the first change of state is not detected until after an additional 25µs The MPI pin has a small pull up device that will source 1 to 4 mA of current from VCC This pin does not require pull up devices or VCC connection if it is not used MULTI PURPOSE OUTPUT PIN This pin can be programmed to serve as a request to send output t...

Page 10: ... the receiver has sampled the stop bit indicated in auto echo by assertion o fRxRDY and the transmitter is enabled the transmitter is enabled the transmitter will remain in auto echo mode until one full stop bit has been retransmitted MR2 5 Transmitter Request to Send Control CAUTION When the transmitter controls the OP pin usually used for the RTSN signal the meaning of the pin is not RTSN at all...

Page 11: ...Yes 0 No 1 Yes 0 No 1 Yes NOTE Access to the miscellaneous commands should be separated by 3 X1 clock edges A disabled transmitter cannot be loaded SR Channel Status Register Received Break Framing Error Parity Error Overrun Error TxEMT TxRDY FFULL RxRDY 0 No 1 Yes 0 No 1 Yes 0 No 1 Yes 0 No 1 Yes 0 No 1 Yes 0 No 1 Yes 0 No 1 Yes 0 No 1 Yes NOTE These status bits are appended to the corresponding ...

Page 12: ...ror framing error and overrun error bits in the status register SR 7 4 Used in character mode to clear OE status although RB PE and FE bits will also be cleared and in block mode to clear all error status after a block of data has been received 0101 Reset break change interrupt Causes the break detect change bit in the interrupt status register ISR 3 to be cleared to zero 0110 Start break Forces t...

Page 13: ...e set when the transmitter is first enabled and at any time it is re enabled after either a reset or b the transmitter has assumed the disabled state It is always set after transmission of the last stop bit of a character if no character is in the THR awaiting transmission It is reset when the THR is loaded by the CPU a pending transmitter disable is executed the transmitter is reset or the transm...

Page 14: ...yn chronized 1X clock is output 101 The 16X clock for the receiver This is the clock selected by CSR 7 4 and is a 1X clock if CSR 7 4 1111 110 The transmitter register empty signal which is the comple ment of SR 2 Active low output 111 The receiver ready or FIFO full signal complement of ISR 2 Active low output ISR Interrupt Status Register This register provides the status of all potential interr...

Page 15: ...igital divider Therefore 26 would be chosen This gives a baud rate error of 0 3 26 3 which is 1 14 well within the ability asynchronous mode of operation If the value in CTUR or CTLR is changed the current half period will not be affected but subsequent half periods will be The counter ready status bit ISR 4 is set once each cycle of the square wave The bit is reset by a stop counter command The c...

Page 16: ...midpoint of the switching signal VM to a point 0 5V above VOL This point represents noise margin that assures true switching has occurred Beyond this level the effects of external circuitry and test environment are pronounced and can greatly affect the resultant measurement SD00126 Figure 6 Interrupt Timing X1 CLK C T CLK RxC TxC tCLK tCTC tRx tTx tCLK tCTC tRx tTx C1 C2 Y1 X1 CLK X2 SCC2691 Y1 3 ...

Page 17: ...a sheet SCC2691 Universal asynchronous receiver transmitter UART 2006 Aug 04 17 tTXD tTCS 1 BIT TIME 1 OR 16 CLOCKS TxD TxC INPUT TxC 1X OUTPUT SD00092 Figure 8 Transmit Timing tRXS tRXH RxC 1X INPUT RxD SD00093 Figure 9 Receive Timing ...

Page 18: ...BE TRANSMITTED D6 CR 7 4 1010 CR 7 4 1010 NOTES 1 TIMING SHOWN FOR MR2 4 1 2 TIMING SHOWN FOR MR2 5 1 SD00128 Figure 10 Transmitter Timing D1 D2 D4 D5 D6 D7 D8 D3 RxD RECEIVER ENABLED RxRDY SR0 FFULL SR1 RxRDY RDN OVERRRUN SR4 RTS1 MPO NOTES 1 Timing shown for MR1 7 2 Shown for ACR 2 111 and MR1 6 0 FFULL MPO2 MPO 1 CR 7 4 1010 RESET BY COMMAND D5 WILL BE LOST S D S D S D S D D2 D3 D4 D1 S STATUS ...

Page 19: ...a point of confusion arises in that MP0 may also be controlled by the transmitter When the transmitter is controlling this pin its meaning is not RTS at all It is rather that the transmitter has finished sending its last data byte Programming the MP0 pin to be controlled by the receiver and the transmitter at the same time is allowed but would usually be incompatible RTS can also be controlled by ...

Page 20: ... for SCN2681 SCN68681 SCC2691 SCC2692 SCC68681 and SCC2698B in application notes elsewhere in this publication The test mode at address H A changes all transmitters and receivers to the 1x mode and connects the output ports to some internal nodes Receiver Reset in the Normal Mode Receiver Enabled Reset can be accomplished easily by issuing a receiver software or hardware reset followed by a receiv...

Page 21: ...Philips Semiconductors Product data sheet SCC2691 Universal asynchronous receiver transmitter UART 2006 Aug 04 21 DIP24 plastic dual in line package 24 leads 300 mil SOT222 1 ...

Page 22: ...Philips Semiconductors Product data sheet SCC2691 Universal asynchronous receiver transmitter UART 2006 Aug 04 22 SO24 plastic small outline package 24 leads body width 7 5 mm SOT137 1 ...

Page 23: ...Philips Semiconductors Product data sheet SCC2691 Universal asynchronous receiver transmitter UART 2006 Aug 04 23 PLCC28 plastic leaded chip carrier 28 leads SOT261 2 ...

Page 24: ... Date Description _3 20060804 Product data sheet 9397 750 14951 Supersedes data of 1998 Sep 04 9397 750 04358 Modifications Ordering information changed Version for PLCC28 from SOT261 3 to SOT261 2 Changed package outline drawing from SOT261 3 to SOT261 2 _2 19980904 Product specification 9397 750 04358 ECN 853 1078 19971 _1 19950501 ...

Page 25: ...anted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage Philips Semiconductors accepts no liability for inclusion and or use of Philips Semiconductors products in such equipmen...

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