Circuit Diagrams and PWB Layouts
10.
SSB: PNX5100 - Power
VSS
VDD_3V3_PER
VSS
VDD_3V3_LVDSOUT
VDD_1V8_DDR
VSS
VDD_3V3_LVDSIN
VDD_1V2_CORE
VSS
VSS
COM
OUT
IN
C
FC82 E8
FC83 E8
FC84 F8
FC85 F8
FC86 D10
FC87 E10
FC88 E10
FC89 F10
FC90 F10
BD 12NC : 3139_123_64431
MULTI 12NC : 3139_123_64421
CELL 12NC : 8239_125_14781
5
" XC90 ~ XC9Z "
5C70 F10
5C71 E2
5C72 E2
5C73 F2
7C00-10 C5
7C00-11 A8
7C60 A3
CC60 B4
FC60 B4
10
1
4
3
E
5
7
1
PNX5100 - POWER
G
FC61 G6
FC80 D8
FC81 E8
owner.
A
2C96 B3
2C97 B3
2C98 B3
2C99 B4
5C60 D7
5C61 E7
5C62 E7
D
C
J
8
12
11
" XC80 ~ XC8Z "
D
E
B
6
" XC60 ~ XC6Z "
5C63 E7
5C64 F7
5C65 F7
5C66 D10
5C67 E10
5C68 E10
5C69 F10
2C87 E10
2C88 E10
2C89 F10
2C90 F10
2C91 F10
2C92 F10
2C93 B2
2C94 F8
2C95 B3
J
8
3
2
" XC50 ~ XC5Z "
7
F
" XC70 ~ XC7Z "
C
11
12
13
2C70-2 E4
2C70-3 E4
2C70-4 E4
2C71 F3
2C72 F3
2C73 F3
2C74 F3
2C75 F4
2C76 F4
F
2
G
is prohibited without the written consent of the copyright
2C77 D10
2C78-1 C2
2C78-2 C2
2C78-3 C2
2C78-4 E4
2C79 D7
2C80 D8
2C81 C4
2C82 F8
2C83 G8
2C84 E10
2C85 E10
2C86 E10
2C63-4 C4
2C64 C4
2C65 C5
2C66-1 D3
2C66-2 D3
2C66-3 D3
2C66-4 D3
2C67-1 D3
2C67-2 D3
I
6
I
B
10
9
2C67-3 D4
2C67-4 D4
2C68-1 E3
2C68-2 E3
2C68-3 E3
2C68-4 E3
2C69-1 E3
2C69-2 E3
2C69-3 E4
2C69-4 E4
2C6A B4
2C70-1 E4
5
6
7
8
9
10
11
12
A
H
13
H
9
All rights reserved. Reproduction in whole or in parts
2C57 E10
2C58 F10
2C59 B2
2C60-1 C2
2C60-2 C2
2C60-3 C2
2C60-4 C3
2C61-1 C3
2C61-2 C3
2C61-3 C3
2C61-4 C3
2C62-1 C3
2C62-2 E8
2C62-3 C4
2C62-4 E8
2C63-1 C4
2C63-2 C4
2C63-3 F8
B
C
D
E
F
G
H
2C55 E2
2C56 E2
4
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
45
A
B
C
D
E
F
G
H
A
18
100n
2C66-4
100n
2C67-1
100n
2C68-3
36
2C68-2
100n
27
45
2C97
10u
2C67-4
100n
2C82
100n
100n
2C70-1
18
5C64
30R
8
100n
2C60-1
1
10u
2C93
2C70-4
100n
45
+1V2-PNX5100-DLL
+1V2-PNX5100-TRI-PLL2
+1V2-PNX5100-TRI-PLL3
+3V3-PNX5100-DDR-PLL0
5C73
30R
+3V3F
5C72
30R
5C71
30R
2C72
100n
2C65
100n
45
100n
2C64
2C63-4
100n
2C76
100n
18
+1V2-PNX5100
+3V3-PNX5100-LVDS-PLL
4
100n
2C63-1
6
100n
2C62-4
2C62-3
100n
3
100n
2C62-2
2
2C61-3
100n
36
36
FC85
100n
2C70-3
+1V2-PNX5100-DDR-PLL1
2C95
10u
100n
2C94
+1V2-PNX5100
2C79
100n
10u
2C55
30R
5C68
AC2
AC3
AC4
+3V3
AC1
R23
R25
T11
T12
T13
T14
T15
V25
W23
AE26
P12
P13
P14
P15
P23
R11
R12
R13
R14
R15
M13
M14
M15
M25
N11
N12
N13
N14
N15
P11
AB5
F25
H23
J25
L11
L12
L13
L14
L15
M11
M12
AB4
B2
A20
C2
C25
C3
D3
D4
E4
E5
AB3
AD2
AD24
AD3
AE1
AE2
AF1
B1
A10
A13
AA25
A17
AB6
AB7
D22
E6
E7
G5
M5
N5
A1
AD1
R16
T16
AB15
AB17
D10
D13
D17
D20
AB20
V5
W5
AB9
AC9
AD9
AE9
AF9
E16
L16
M16
N16
P16
AA5
E8
E9
F5
J22
K22
P5
R5
Y5
AB16
AB8
Φ
SUPPLY_1
PNX5100E
7C00-10
2C78-4
100n
45
+1V2-PNX5100
5C61
30R
+1V2-PNX5100-TRI-PLL1
18
100n
2C68-1
30R
5C65
+1V2-PNX5100-LVDS-PLL
+1V2-PNX5100-CLOCK
+1V2-PNX5100
+1V2-PNX5100
27
+1V2-PNX5100
2C63-2
100n
FC60
2C90
100n
5C69
30R
+3V3-PNX5100-LVDS-IN
+3V3
AB13
VSS_MCAB2
+1V8-PNX5100
+3V3
U4
VSSA_TRI_PLL3
AE12
VSSA_XTAL
J3
VSSD_TRI_PLL1
K3
VSSD_TRI_PLL2
U3
VSSD_TRI_PLL3
AD26
VSS_DDRPLL0
R22
VSS_DDRPLL1
AC13
VSS_MCAB1
AB22
VSSA_DLL1
E22
VSSA_DLL4
U22
VSSA_DLL7
A15
VSSA_LVDS1
C15
VSSA_LVDS2
AB19
VSSA_LVDSIN
J4
VSSA_TRI_PLL1
K4
VSSA_TRI_PLL2
K5
VDDD_1V2_TRI_PLL2
U5
VDDD_1V2_TRI_PLL3
AD25
VDD_1V2_DDRPLL0
N22
VDD_1V2_DDRPLL1
AB14
VDD_1V2_MCAB1
AC14
VDD_1V2_MCAB2
T22
VSSA_DDRPLL1
L22
VSSA_DLL0
AF12
VDDA_1V2_UIP_PLL
AD13
VDDA_1V2_XTAL
AE25
VDDA_3V3_DDRPLL0
B15
VDDA_3V3_LVDS1
D15
VDDA_3V3_LVDS2
AB18
VDDA_3V3_LVDSIN
AD14
VDDA_3V3_SYS_PLL
H5
VDDD_1V2_TRI_PLL1
M22
VDDA_1V2_DLL0
AA22
VDDA_1V2_DLL1
F22
VDDA_1V2_DLL4
V22
VDDA_1V2_DLL7
E15
VDDA_1V2_LVDS_PLL
J5
VDDA_1V2_TRI_PLL1
L5
VDDA_1V2_TRI_PLL2
T5
VDDA_1V2_TRI_PLL3
SUPPLY_2
Φ
PNX5100E
7C00-11
AE14
VDDA_1V2_1_7_MCAB
P22
VDDA_1V2_DDRPLL1
+1V2-PNX5100-DLL
+3V3-PNX5100-CLOCK
+3V3-PNX5100-LVDS-IN
+1V2-PNX5100-TRI-PLL1
5C67
30R
2C78-1
100n
18
30R
5C60
36
+1V2-PNX5100-CLOCK
+1V2-PNX5100
100n
2C67-3
100n
45
+1V2-PNX5100
18
2C68-4
2C62-1
100n
FC83
FC81
2C59
330u
6.3V
2C81
100n
2C60-2
100n
27
+1V2-PNX5100
+1V2-PNX5100
+3V3
27
18
100n
2C69-2
2C69-1
100n
+1V2-PNX5100-DLL
5C66
30R
+1V2-PNX5100
FC61
+1V2-PNX5100-LVDS-PLL
2C57
10u
2C92
100n
+1V2-PNX5100-CLOCK
+3V3-PNX5100-LVDS-PLL
100n
2C91
2C6A
10u
45
36
100n
2C69-4
+1V2-PNX5100
2C69-3
100n
2C78-3
100n
36
100n
2C87
100n
2C71
100n
2C85
100n
2C98
2C58
100n
100n
2C83
5C70
30R
100n
2C74
2C73
100n
2C70-2
100n
27
+1V2-PNX5100
+1V2-PNX5100
+1V2-PNX5100-TRI-PLL2
30R
5C62
100n
2C75
2C84
100n
2C67-2
100n
27
3
100n
2C63-3
2C86
100n
2C56
10u
100n
2C60-3
36
2C60-4
100n
45
2C61-1
100n
18
27
100n
2C61-2
22u
2C99
FC90
FC89
10u
2C96
FC82
FC80
+1V2-PNX5100
CC60
100n
2C77
+1V2-PNX5100-DDR-PLL1
+3V3-PNX5100-DDR-PLL0
+3V3-PNX5100-CLOCK
2C88
100n
2C66-3
100n
36
27
100n
18
100n
2C78-2
27
2C66-1
+1V8-PNX5100
100n
2C66-2
+3V3
+3V3
+3V3
45
2009-01-16
DC343514
Vincent Yap / Lee CW
2009-01-16
2
3
100n
2C61-4
-- -- --
2008-10-07
A3
PCB SB SSB BD
TV543_2K9
3139 123 6443
CHECK
DATE
NAME
1
SUPERS.
1
CLASS_NO
*
*
*
*
*
*
*
*
E
M
A
N
T
E
S
N
H
C
25
3PC332
21
2008-10-17
ROYAL PHILIPS ELECTRONICS N.V. 2008
**** *** *****
SV
130
10
1
2008-12-16
FC87
100n
2C89
LD1117DT18
7C60
1
3
2
FC86
FC84
5C63
30R
+1V2-PNX5100-TRI-PLL3
FC88
100n
2C80
SENSE+1V2-PNX5100
1
8
440_520_090224
.ep
s
090224