5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
CRYSTAL
RESET CIRCUIT
CMOS SERIES ONLY.
升级口
Crystal Circuit
20080408
20080408
20080408
20080408
20080516
DSU
PIN1
PIN128
PIN27
上拉
4.7K
到
3.3V
PET988
Ver A1
MPEG
D
2
7
Wednesday, August 06, 2008
Title
Size
Document Number
Rev
Date:
Sheet
of
P9
+3.3V
+1.8V
RF_SCK
OEV
PCK1
AOUT_L
DACR
CKV
AOUT_R
RF_SDA
DACG
TEI
STHL
MIRR
OEH
FEI
CVBS
MCLK
SD_DAT0
SDCMD/MSBC
MNTR
RF_SDEN
DACB
RFO
MBA0
SMOTOR
POL
LATCH_D0
STVD
SF_DIO
STRACK
MDQM
SF_SCN
SFOCUS
MBA1
MA
8
MD
7
MA
7
MD
5
MD
1
5
MD
1
3
MA
1
1
MD
4
/u
PRST
P9
KS_CLK
GPC0
KS_DET0
MA
9
MA
1
0
MD
1
4
MA
5
MD
1
IR
/WE
MD
2
MD
1
0
MD
3
XTAL
O
SF_CLK
KS_DATA
MD
8
XTAL
I
SDCLK
SLPWM
MA
2
/RAS
MA
4
MA
1
DN
MD
6
MD
0
MD
1
2
MD
1
1
MD
9
MA
6
MA
3
/CAS
SF_DOA
SPDPWM
MA
0
BLK
TX
RX
/uPRST
QG
QF
QE
QB
QD
QC
KS_CLK
QA
KS_DATA
QH
PWE#
QD
MOCTL-
KS_DET0
QH
164_QH
HOMESW
TX
KS_DET1
RX
XO1
XI1
XI1
DATA
KS_CLK
QA
AV_SW
QD
QG
LATCH_D0
QB
QH
SSPDON
QC
QF
LDON
QE
PWE#
CD_DVDSW
TRAY IN
+5V
RESET-T
SBAD
+5V
GND
AMP_B
AMP_G
AMP_R
PCK1
DCPWM3
STHL
OEH
OEV
STVD
POL
DCPWM2
DC_FBK2
GND
VGL
VGH
GND
GND
+9VIN
DATA
KS_CLK
RESET-T
+3.3V
VGH
VGL
+9VIN
VDD
AMP_B
AMP_R
AMP_G
QB
QC
TRAY IN
DATA
DP
9V
CKV
CLK
CLK
IR
9V
DN
DP
SSLED
SF_DIO
3
+3.3V
1,3,4
SF_SCN
3
+1.8V
1
MBA0
3
RFO
3
AOUT_L
4
SMOTOR
3
MDQM
3
STRACK
3
RF_SDA
3
MIRR
3
FEI
3
SDCMD/MSBC
3
RF_SDEN
3
MNTR
3
CVBS
4
RF_SCK
3
TEI
3
SFOCUS
3
AOUT_R
4
MCLK
3
MD[0..15]
3
SF_DOA
3
/RAS
3
SDCLK
3
SF_CLK
3
/CAS
3
/WE
3
MA[0..11]
3
MBA1
3
KS_CLK
4
LATCH_D0
KS_DET0
3
CD_DVDSW
3
LDON
3
SSPDON
3
KS_CLK
4
LATCH_D0
MOCTL-
3
PWE#
3
HOMESW
3
SD_DAT0
3
MUTE
4
+5V
1,3,4
SBAD
3
VGL
1
VGH
1
+9VIN
1,4
VDD
1,3,4
DATA
4
9V
1
DN
3
DP
3
SSLED
3
+3.3VPA
DGND
+3.3V
AGND
GND
DGND
SGND
DGND
VGND
USB_GND
DGND
AGND
+3.3VA
DGND
MGND
+3.3VA
VREF165
SGND
AGND
SGND
VGND
+3.3VV
+3.3VDDC
+3.3VS
+3.3VV
+1.8VPA
VGND
+3.3V
VAMP
+3.3V
VGND
AGND
VGND
DGND
+3.3V
+3.3
DGND
VAMP
+5V
VGND
VDD
VDD
DGND
DGND
DGND
DGND
DGND
+3.3VDDC
+3.3VA
ADGND
ADGND
+1.8V
+1.8V
+1.8V
+3.3VS
AGND
+3.3V
+3.3V
+3.3V
ADGND
+3.3V
+5V
AGND
AGND
VGND
5V
5V
5V
DGND
R25
75K
C32
330p
C31
100n
TP4
CLOCK
C28
100n
C51
27pF
C25
1uf
L9
FB/0805
R
112
100K
J3
TO DRIVER BOARD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
C30
100n
TP5
T
U5
74HC164
1
2
8
9
3
4
5
6
10
11
12
13
14
7
A
B
CLK
CLR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
VCC
GND
Q8
3906
2
1
3
U6
74LS373
1
10
20
11
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
OE
GND
V
CC
LE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
L7
FB 600R
C50
3.3pF
C47
100n
R32
33
C23
1uf
R18
0
+
EC6
47u/10V
1
2
R
112
100
R30 1M
TP3 PWE#
+
BT1
MS621F
C38
10uf/10v
1
2
R33
4.7K
R125
47R
C121
1uF
C17
100n
D17
BAT54C
1
2
3
R124
1K
C20
100n
R37
4.7k
C44
100n
R24
56K
R
112
100K
L8
FB 600R
U16
1117-3.3V
2
1
3
4
OUT
GND
IN
OUT
C18
100n
C39
100n
C33
200p
C26
100n
+
EC10
47u/16V
C29
680p
C42
1uF
TP2
R21
33R
IR1
1
2
3
DET
GND
VCC
R8
4.7k
R53
10K
YM1
27M
R23
15K
R123
47R
L6
FB/0805
C19
100n
+
EC8
47u/10V
1
2
U7
PT7C4337
1
2
3
4
5
6
7
8
INT1-
XOUT
XIN
VSS
INT2-
SCL
SDA
VDD
C34
0.01uf
TP1 AV_SW
C1
1uF
R
112
100K
C24
1uf
R38
4.7k
Q21
3906
2
1
3
C
107
0.
1U
F
R22
470
C49
100n
SW1
1
2
4
3
C36
100n
R20
33R
C119
100n
C22
100n
R27
10k
R35
4.7k
C46
27p
C35
0.1uf
C16
100n
Q9
3906
2
1
3
R28
6.04K
R39
1K
C
4
1
100n
C
3
7
100n
R34
1K
C27
100n
D10
RLS4148
R
112
100K
+
EC38
47u/10V
1
2
R13 100
R19
33R
R26
10K
R36
4.7k
J2
PIN HEADER 1X4
1
2
3
4
C45
27p
D7
RLS4148
+
EC5
47u/10V
CT909P-W
U4
CT909P-W
1
121
22
23
24
25
26
27
28
29
30
31
32
2
3
4
5
6
7
8
9
10
11
12
15
13
14
16
17
18
47
19
20
21
33
34
35
36
45
44
43
42
41
39
38
37
46
40
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
97
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
103
88
89
90
91
92
93
94
95
96
98
99
100
101
102
104
105
106
107
108
109
110
111
112
113
114
116
115
117
118
119
120
122
123
124
125
126
127
128
GPC[6
]/SDCL
K/DSU1
_
T
X
VDD18
G
P
C[5
]/KEY_
DET1
/UR2
_
R
X
GPC[4
]/D_
L
A
T
CH1
/PW
E
/UR2
_
T
X
GPC[3
]/D_
L
A
T
CH0
GPC[2
]/KS_
CL
K
GPC[1
]/KS_
DAT
A
G
P
C[0
]/KEY_
DET0
GPA[0
]/SF
_
CSN/F
A
[0
]/UR1
_
R
X/DSU2
_
R
X
G
PA[1
]/SF_
CL
K/FA[1
]/UR1
_
T
X/DSU2
_
T
X
G
PA[2
]/SF_
DIO
/FA[2
]/DSU1
_
R
X/UR2
_
R
X
G
PA[3
]/SF_
DO
/FA[3
]/DSU1
_
T
X/UR2
_
T
X
VSS
P
LL2_
VSS3
P
LL2_V
LF
P
LL_V
D
D
3
P
LL1_V
LF
P
LL1_
VSS3
VBUS
ID
USB_
AVDD3
DN
DP
USB_
AVSS3
USB_
AVSS1
8
RREF
EXT
USB_
AVDD1
8
VDD1
8
XTAL
I
XTAL
O
AAVDD3
D
FTEN
RESET_
N
IR
DCF
BK2
DCF
BK1
DCPW
M
2
DCPW
M
1
GPD[6]/CPH1/PCLK
GPD[8]/CPH3(R1)/STVU/DCPWM3
GPD[0]/STHL
GPD[1]/OEH(LP)/PDE
GPD[5]/OEV/TC_GPO0
GPD[4]/CLKV/PVS
G
P
D[3
]/STVD
G
P
D[2
]/PO
L
/PHS
GPE[0]/SPDIF
VDD3
AAVSS
AMID
AAVSS
ADAC1L
ADAC2R
AAVSS
VREF
FSADJ
VD_AVSS3
CVBS
VD_AVDD3
R
VD_AVSS3
G
VD_AVDD3
B
VD_AVSS3
HIV_
VSS5
HIV_
R
HIV_
G
HIV_
B
HIV_
VDD5
VDD1
8
MD
[0
]
MD
[1
]
MD
[2
]
MD
[3
]
MD
[4
]
MD
[5
]
MD
[6
]
MD
[7
]
MD
QM
VDD3
M
D
[15]
M
D
[14]
M
D
[13]
M
D
[12]
M
D
[11]
M
D
[10]
MD
[9
]
MD
[8
]
MA[10]
VSS
MC
L
K
M
A
[1
1
]/M
CS[0
]_
N/G
P
H[0
]
MA
[9
]
MA
[8
]
MA
[7
]
MA
[6
]
MA
[5
]
MA
[4
]
MW
E
_
N
M
C
AS_
N
M
R
AS_
N
M
BA[0
]
M
BA[1
]/M
CS[1
]_
N/G
P
H[1
]
MA[0]
MA[1]
MA[2]
MA[3]
SV_AVDD3
RFIN
LE
FE
TE
RFENV
FS
FODAC
SRVM
TRDAC
SV_AVSS3
GPB[0]/SLPWM/NIMDATA
GPB[1]/SPDPWM/NIMPWM
GPB[2]/SDEN/NIMVLD
GPB[3]/SDATA
GPB[4]/SCLK/NIMCLK
GPB[5]/MIRR/NIMSYN
VDD3
GPC[8]/SD_DAT0/DSU1_RX/UR1_RX
GPC[7]/SDCMD/MSBC/UR1_TX
R31
1K
R
112
100K
Y1
32.768KHz
Summary of Contents for PET988
Page 8: ...3 0 INSTRUCTION FOR USE ...
Page 9: ...3 0 INSTRUCTION FOR USE ...
Page 17: ...5 0 TROUBLESHOOTING SYMPTOM NO SOUND FROM HEADPHONE ...
Page 20: ...6 0 BLOCK DIAGRAM ...
Page 28: ......
Page 29: ......
Page 30: ......
Page 31: ......
Page 38: ...9 0 REVISION LIST Version 1 0 3141 785 33140 Initial release PET988 12 ...
