5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
H/W config pin, must always
reserve
These pins must be pull up or pull down
only for test
3.3V POWER
FOR TUNER
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
MAIN BOARD CIRCUIT DIAGRAM-SPHE6600
SUNIF_D3
6600_CLKIN
R_SUNIF_D2
R_SUNIF_D3
S
U
N
IF
_
G
N
T
6600_RESET
R_SUNIF_D2
6600_RESET_A
R_SUNIF_D0
6600_CLKOUT
T
S
_
E
R
R
6
6
0
0
_
G
P
IO
3
SUNIF_GNT
T
S
_
D
I2
R_SUNIF_D1
6600_RESET_A
TS_DI3
TS_CLK_I
R_SUNIF_D0
SUNIF_FRAME
T
S
_
D
I1
R_SUNIF_D1
6600_SDA
R_SUNIF_CLK
6600_RESET
6600_GPIO1
T
S
_
D
I0
6600_CLKOUT
SUNIF_CLK
S
U
N
IF
_
D
1
TS_VAL_I
SUNIF_D3
S
U
N
IF
_
D
0
T
U
_
R
S
T
_
C
T
R
L
SUNIF_FRAME
R_SUNIF_CLK
TS_DI7
TS_DI4
6600_GPIO3
SUNIF_D0
TS_DI6
RESET_B
6600_SCL
SUNIF_GNT
R_SUNIF_FRAME
S
U
N
IF
_
C
L
K
SUNIF_D2
TUN_PWR_CTRL
R_SUNIF_D3
R_SUNIF_FRAME
R_SUNIF_GNT
S
U
N
IF
_
F
R
A
M
E
6
6
0
0
_
G
P
IO
1
SUNIF_D2
R_SUNIF_GNT
6600_SCL
TS_DI5
6600_CLKIN
SUNIF_D1
T
S
_
S
Y
N
C
_
I
CLKIN
CLKIN
6600_SDA
TS_DI4
TS_DI5
TS_DI6
TS_DI7
TS_DI3
TS_DI1
TS_DI2
TS_DI0
TUN_PWR_CTRL
TS_SYNC_I
TU_RST_CTRL
TS_VAL_I
TS_CLK_I
TS_ERR
6600_SCL
6600_SDA
R_SUNIF_GNT 2
R_SUNIF_D3
2
R_SUNIF_FRAME
2
R_SUNIF_D0
2
R_SUNIF_D2
2
6600_RESET_A 2
R_SUNIF_CLK
2
R_SUNIF_D1
2
RESET_B
2
CLKIN
2
TS_DI7
TS_DI6
TS_DI5
TS_DI4
TS_DI3
TS_DI2
TS_DI1
TS_DI0
TS_SYNC_I
TU_RST_CTRL
TS_VAL_I
TS_CLK_I
TS_ERR
6600_SCL
6600_SDA
GND
GND
6600_+5V
G
N
D
GND
PLLVCC2.5
DVCC2.5
GND
TUN_GND
GND
DVCC2.5
6600_DVCC3
GND
6600_+5V
GND
TUN_GND
VCC1.8
GND
G
N
D
GND
DVCC2.5
TUN_GND
VCC3_SW
6600_DVCC3
6600_DVCC3
6600_DVCC3
P
L
L
V
C
C
2
.5
6
6
0
0
_
D
V
C
C
3
GND
6600_+5V
GND
1V8D
6600_DVCC3
PLLVCC2.5
6600_DVCC3
GND
DVCC2.5
6600_+5V
GND
VCC3_SW
6600_DVCC3
GND
3V3D
U2
SPHE6600
1
2
3
4
5
6
7
8
9
10
11
12
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
25
26
27
28
29
30
31
32
33
35
36
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
34
4
5
4
6
4
7
4
8
TS_D3
TS_D4
TS_D5
TS_D6
TS_D7
TS_CLK
VSS_K0
I2C_SCL/TEST1
I2C_SDA/TEST2
VDD25_K0
TS_VAL
VDD3_O0
G
P
IO
1
4
T
S
_
S
T
A
T
S
_
E
R
R
G
P
IO
0
G
P
IO
1
V
S
S
_
O
0
G
P
IO
2
G
P
IO
3
G
P
IO
4
G
P
IO
5
G
P
IO
6
V
D
D
2
5
_
P
L
L
VSS_PLL
XIN
XOUT
PWM
VSS_K1
CK27O
VDD25_K1
RSTB
INT
SUNIF_D2
GPIO7
V
D
D
3
_
1
S
U
N
IF
_
D
1
S
U
N
IF
_
D
0
S
U
N
IF
_
F
R
A
M
E
S
U
N
IF
_
G
N
T
V
S
S
_
O
1
S
U
N
IF
_
C
L
K
G
P
IO
1
2
SUNIF_D3
G
P
IO
1
3
T
S
_
D
0
T
S
_
D
1
T
S
_
D
2
R24
47K
C5
NC
R7
0
L1
FB
C8
0.1u
EC2
100u/16V
T
P
9
A
U
D
IO
_
M
U
T
E
EC3
100u/16V
L2
FB
C14
0.1u
R4
470
R3
470
EC1
100u/16V
C2
0.1u
U1 AMS1085 TO-252
1
3
2
A
D
J
IN
OUT
R2
0
C1
0.1u
R19
4.7K
R1
10
R20
10K
C9
0.1uF
R21
10K
R8
NC
C12
0.1uF
R25
47K
C11
0.1uF
C13
0.1uF
R13
0
R9
0
R11
0
R22
10K
R15
NC
R23
10K
R14
0
Q2
2N3904
RN1
0(8P4R)
7
5
3
1
2
4
6
8
Q1
APM2301AAC
2
3
1
C7
27pF
R17
4.7K
R6
1K
C6
27pF
XT1
27MHz
R18
100K
R5
10K
R10
0
C10
0.1uF
R16
0
R12
0
C3
NC
C4
NC
Summary of Contents for PET745/12
Page 7: ...3 0 INSTRUCTION FOR USE ...
Page 8: ...3 0 INSTRUCTION FOR USE ...
Page 27: ...MAIN BOARD TOP ...
Page 28: ...MAIN BOARD BOTTOM ...
Page 29: ...TFT BOARD TOP ...
Page 30: ...TFT BOARD BOTTOM ...
Page 31: ...DC IR BOARD TOP ...
Page 32: ...DC IR BOARD BOTTOM ...