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Philips Semiconductors

User’s Manual - Preliminary -

P89LPC906/907/908

CLOCKS

2003 Dec 8

25

2. CLOCKS

ENHANCED CPU

The

P89LPC906/907/908

uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine

cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

CLOCK DEFINITIONS

The

P89LPC906/907/908

device has several internal clocks as defined below:

• OSCCLK - Input to the DIVM clock divider. OSCCLK is selected from one of the clock sources (see Figure 2-3,Figure 2-4,) and

can also be optionally divided to a slower frequency (see section "CPU Clock (CCLK) Modification: DIVM Register").

Note

:

f

OSC

is defined as the OSCCLK frequency.

• XCLK - Output of the crystal oscillator (

P89LPC906

)

• CCLK - CPU clock .
• PCLK - Clock for the various peripheral devices and is CCLK/2

CPU CLOCK (OSCCLK)

The

P89LPC906

provides several user-selectable oscillator options. This allows optimization for a range of needs from high

precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip
watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal
oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.

The

P89LPC907

and

P89LPC908

devices allow the user to select between an on-chip watchdog oscillator and an on-chip RC

oscillator as the CPU clock source.

LOW SPEED OSCILLATOR OPTION - P89LPC906

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this
configuration.

MEDIUM SPEED OSCILLATOR OPTION - P89LPC906

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this
configuration.

HIGH SPEED OSCILLATOR OPTION - P89LPC906

This option supports an external crystal in the range of 4MHz to 12 MHz. Ceramic resonators are also supported in this
configuration. If CCLK is 8MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ’1’ to reduce power consumption. On
reset, CLKLP is ’0’ allowing highest performance access. This bit can then be set in software if CCLK is running at 8MHz or
slower.

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Summary of Contents for P89LPC906

Page 1: ...EGRATED CIRCUITS Philips Semiconductors PHILIPS 2003 Dec 8 P89LPC906 907 908 8 bit microcontrollers with accelerated two clock 80C51 core 1KB 3V Low Power byte eraseable Flash with 128 Byte RAM USER MANUAL ...

Page 2: ...er the CLKLP SFR bit AUXR1 7 can be set to 1 to re duce power consumption On reset CLKLP is 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8MHz or slower 26 Watchdog Oscillator Option 26 External Clock Input Option P89LPC906 27 CPU Clock CCLK Wakeup Delay 27 CPU Clock CCLK Modification DIVM Register 27 Low Power Select P89LPC906 28 29 3 Interrupts ...

Page 3: ...61 More About UART Mode 0 63 More About UART Mode 1 64 More About UART Modes 2 and 3 65 Framing Error and RI in Modes 2 and 3 with SM2 1 65 Break Detect 65 Double Buffering 66 Double Buffering in Different Modes 66 Transmit Interrupts with Double Buffering Enabled Modes 1 2 and 3 66 The 9th Bit Bit 8 in Double Buffering Modes 1 2 and 3 67 Multiprocessor Communications 68 Automatic Address Recognit...

Page 4: ...tures 87 Software Reset 87 Dual Data Pointers 87 14 Flash program memory 89 General description 89 Features 89 Introduction to IAP Lite 89 Using Flash as data storage 89 Accessing additional flash elements 92 Erase programming additional flash elements 93 Reading additional flash elements 93 User Configuration Bytes 96 User Security Bytes 97 Boot Vector 98 Boot Status 98 15 Instruction set 99 16 R...

Page 5: ...nal Output 36 Open Drain Output 36 Input Only 37 Push Pull Output 37 Port Output Configuration P89LPC906 38 Port Output Configuration P89LPC907 38 Port Output Configuration P89LPC908 38 Additional Port Features 38 Timer Counter Mode Control register TMOD 41 Timer Counter Auxiliary Mode Control register TAMOD 42 Timer Counter Control register TCON 43 Timer Counter 0 or 1 in Mode 0 13 bit counter 44...

Page 6: ...pad Control Register 77 Keypad Interrupt Mask Register KBM 78 Watchdog timer configuration 79 Watchdog Prescaler 80 Watchdog Timer Control Register 81 P89LPC906 907 908 Watchdog Timeout Values 82 Watchdog Timer in Watchdog Mode WDTE 1 83 Watchdog Timer in Timer Mode WDTE 0 84 AUXR1 Register 87 Flash Memory Control Register 91 Assembly language routine to erase program all or part of a page 92 C la...

Page 7: ...executes instructions six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC906 907 908 in order to reduce component count board space and system cost PIN CONFIGURATIONS 8 Pin Packages CLKOUT XTAL2 P3 0 1 2 3 4 8 7 6 5 VSS VDD XTAL1 P3 1 P0 5 CMPREF KBI5 P0 4 CIN1A KBI4 P89LPC906 P0 6 CMP1 KBI6 RST P1 5 1 2 3 4 8 7 6 5 RST P1 5 VSS VDD P0 6 ...

Page 8: ...hree devices Part number Ext crystal pins CLKOUT output T0 PWM output Analog comparator UART TxD RxD P89LPC906 X X X P89LPC907 X X X P89LPC908 X X X VDD VSS PORT1 PORT0 P89 LPC906 CIN1A CMPREF KBI4 KBI5 CLKOUT XTAL1 RST XTAL2 PORT3 VDD VSS PORT1 PORT0 P89 LPC907 CIN1A CMPREF KBI4 KBI5 KBI6 RST CMP1 VDD VSS PORT1 PORT0 P89 LPC908 CIN1A CMPREF KBI4 KBI5 KBI6 RST CMP1 RxD TxD CMP1 KBI6 T0 TxD ...

Page 9: ... Port 0 Configurable I Os 128 byte Data RAM 1 KB Code Flash Internal Bus Timer0 Timer1 Keypad Interrupt Power Monitor Power On Reset Brownout Reset Configurable Oscillator Crystal or Resonator On Chip RC Oscillator Programmable Oscillator Divider CPU Clock Port 1 Input Port 3 Configurable I Os Watchdog Timer and Oscillator Analog Comparator Real Time Clock System Timer ...

Page 10: ...e I Os 128 byte Data RAM 1 KB Code Flash Internal Bus Timer0 Timer1 Keypad Interrupt Power Monitor Power On Reset Brownout Reset On Chip RC Oscillator Programmable Oscillator Divider CPU Clock Port 1 Configurable I O Watchdog Timer and Oscillator Analog Comparator Real Time Clock System Timer UART High Performance Accelerated 2 clock 80C51 CPU ...

Page 11: ... I Os 128 byte Data RAM 1 KB Code Flash Internal Bus Timer0 Timer1 Keypad Interrupt Power Monitor Power On Reset Brownout Reset On Chip RC Oscillator Programmable Oscillator Divider CPU Clock Port 1 Configurable I Os Watchdog Timer and Oscillator UART Analog Comparator Real Time Clock System Timer High Performance Accelerated 2 clock 80C51 CPU ...

Page 12: ...ess 0 Also used during a power on sequence to force In Circuit Programming mode P3 0 P3 1 4 5 I O Port 3 Port 3 is an I O port with a user configurable output types During reset Port 3 latches are configured in the input only mode with the internal pullups disabled The operation of port 3 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independen...

Page 13: ...Port 1 Port 1 is an I O port with a user configurable output types During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to the section Port Configurations on page 35 and...

Page 14: ...1 0 P1 5 1 4 5 Port 1 Port 1 is an I O port with a user configurable output types During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to the section Port Configurations...

Page 15: ...2 E1 E0 ACC Accumulator E0H 00H 00000000 AUXR1 Auxiliary Function Register A2H CLKLP ENT0 SRST 0 DPS 00H1 000000x0 F7 F6 F5 F4 F3 F2 F1 F0 B B Register F0H 00H 00000000 CMP1 Comparator 1Control Register ACH CE1 CN1 OE1 CO1 CMF1 00H1 xx000000 DIVM CPU Clock Divide by M Control 95H 00H 00000000 DPTR Data Pointer 2 bytes DPH Data Pointer High 83H 00H 00000000 DPL Data Pointer Low 82H 00H 00000000 FMA...

Page 16: ...1 00000000 P3M1 Port 3 Output Mode 1 B1H P3M1 1 P3M1 0 03H1 xxxxxx11 P3M2 Port 3 Output Mode 2 B2H P3M2 1 P3M2 0 00H1 xxxxxx00 PCON Power Control Register 87H BOPD BOI GF1 GF0 PMOD1 PMOD0 00H 00000000 PCONA Power Control Register A B5H RTCPD VCPD 00H1 00000000 D7 D6 D5 D4 D3 D2 D1 D0 PSW Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P 00H 00000000 PT0AD Port 0 Digital Input Disable F6H PT0AD 5 PT...

Page 17: ... 00000000 TMOD Timer 0 and 1 Mode 89H T1M1 T1M0 T0M1 T0M0 00H 00000000 TRIM Internal Oscillator Trim Register 96H ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM 0 Notes 4 5 WDCON Watchdog Control Register A7H PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK Notes 3 5 WDL Watchdog Load C1H FFH 11111111 WFEED1 Watchdog Feed 1 C2H WFEED2 Watchdog Feed 2 C3H Name Description SFR Address Bit Functions and Addresses Res...

Page 18: ...Data Pointer 2 bytes DPH Data Pointer High 83H 00H 00000000 DPL Data Pointer Low 82H 00H 00000000 FMADRH Program Flash Address High E7H 00H 00000000 FMADRL Program Flash Address Low E6H 00H 00000000 FMCON Program Flash Control Read E4H BUSY HVA HVE SV OI 70H 01110000 Program Flash Control Write FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD 0 FMDATA Program Flash Data E5H 00H 000000...

Page 19: ...wer Control Register A B5H RTCPD VCPD SPD 00H1 00000000 D7 D6 D5 D4 D3 D2 D1 D0 PSW Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P 00H 00000000 PT0AD Port 0 Digital Input Disable F6H PT0AD 5 PT0AD 4 00H xx00000x RSTSRC Reset Source Register DFH BOF POF R_WD R_SF R_EX Note 2 RTCCON Real Time Clock Control D1H RTCF RTCS1 RTCS0 ERTC RTCEN 60H1 5 011xxx00 RTCH Real Time Clock Register High D2H 00H5 ...

Page 20: ...00H 00000000 TMOD Timer 0 and 1 Mode 89H T1M1 T1M0 T0M1 T0M0 00H 00000000 TRIM Internal Oscillator Trim Register 96H TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM 0 Notes 4 5 WDCON Watchdog Control Register A7H PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK Notes 3 5 WDL Watchdog Load C1H FFH 11111111 WFEED1 Watchdog Feed 1 C2H WFEED2 Watchdog Feed 2 C3H Name Description SFR Address Bit Functions and Addresses Reset ...

Page 21: ... Pointer 2 bytes DPH Data Pointer High 83H 00H 00000000 DPL Data Pointer Low 82H 00H 00000000 FMADRH Program Flash Address High E7H 00H 00000000 FMADRL Program Flash Address Low E6H 00H 00000000 FMCON Program Flash Control Read E4H BUSY HVA HVE SV OI 70H 01110000 Program Flash Control Write FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD 0 FMDATA Program Flash Data E5H 00H 00000000 I...

Page 22: ...rd D0H CY AC F0 RS1 RS0 OV F1 P 00H 00000000 PT0AD Port 0 Digital Input Disable F6H PT0AD 5 PT0AD 4 PT0AD 2 00H xx00000x RSTSRC Reset Source Register DFH BOF POF R_BK R_WD R_SF R_EX Note 2 RTCCON Real Time Clock Control D1H RTCF RTCS1 RTCS0 ERTC RTCEN 60H1 5 011xxx00 RTCH Real Time Clock Register High D2H 00H5 00000000 RTCL Real Time Clock Register Low D3H 00H5 00000000 SADDR Serial Port Address R...

Page 23: ...r up reset all reset source flags are cleared except POF and BOF the power on reset value is xx110000 3 After reset the value is 111001x1 i e PRE2 PRE0 are all 1 WDRUN 1 and WDCLK 1 WDTOF bit is 1 after watchdog reset and is 0 after power on reset Other resets will not affect WDTOF 4 On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initia...

Page 24: ...addressing using instructions other than MOVX and MOVC SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing CODE 1KB of Code memory accessed as part of program execution and via the MOVC instruction 1 KB Flash Code Memory Space 0000h 00FFh Sector 0 Sector 1 0100h 01FFh 0200h 02FFh Sector 2 Sector 3 0300h 03FFh Data ...

Page 25: ...are configured when the FLASH is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 12 MHz The P89LPC907 and P89LPC908 devices allow the user to select between an on chip watchdog oscillator...

Page 26: ...r This can be done by reading the contents of the TRIM register into the ACC for example modifying bit 6 and writing this result back into the TRIM register Alternatively the ANL direct or ORL direct instructions can be used to clear or set bit 6 of the TRIM register Increasing the TRIM value will decrease the oscillator frequency ON CHIP RC OSCILLATOR OPTION The P89LPC906 907 908 has a 6 bit fiel...

Page 27: ...orarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events other than those that can cause interrupts i e events that allow exiting the Idle mode by executing its normal program at a lower rate This can often result in lower power consumption than in Idle mode This can allow bypassing the oscillator start up time in case...

Page 28: ...R1 7 can be set to a 1 to lower the power consumption further On any reset CLKLP is 0 allowing highest performance This bit can then be set in software if CCLK is running at 8MHz or slower Figure 2 3 Block Diagram of Oscillator Control P89LPC906 RTC CPU High freq Med freq Low freq Watchdog Oscillator RC Oscillator XTAL1 XTAL2 2 DIVM WDT 7 3728MHz 400KHz CCLK PCLK Timer 0 1 OSC CLK Oscillator Clock...

Page 29: ...LPC906 907 908 CLOCKS 2003 Dec 8 29 Figure 2 4 Block Diagram of Oscillator Control P89LPC907 P89LPC908 RTC CPU W atchdog Oscillator RC Oscillator 2 DIVM W DT 7 3728MHz 400KHz CCLK UART Tim er 0 1 PCLK CPU Clock Baud rate Generator RTCS1 0 OSC CLK FOSC2 0 ...

Page 30: ...Philips Semiconductors User s Manual Preliminary P89LPC906 907 908 CLOCKS 2003 Dec 8 30 ...

Page 31: ...t source If two requests of different priority levels are pending at the start of an instruction the request of higher priority level is serviced If requests of the same priority level are pending at the start of an instruction an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used to resolve pending r...

Page 32: ...Priority Arbitration Ranking Power down Wakeup Timer 0 Interrupt TF0 000Bh ET0 IEN0 1 IP0H 1 IP0 1 3 No Timer 1 Interrupt TF1 001Bh ET1 IEN0 3 IP0H 3 IP0 3 5 No Serial Port Tx and Rx1 3 TI RI 0023h ES ESR IEN0 4 IP0H 4 IP0 4 8 No Serial Port Rx1 3 RI Brownout Detect BOF 002Bh EBO IEN0 5 IP0H 5 IP0 5 1 Yes Watchdog Timer Real time Clock WDOVF RTCF 0053h EWDRT IEN0 6 IP0H 6 IP0 6 2 Yes KBI Interrupt...

Page 33: ...LPC906 Figure 3 2 Interrupts sources enables and Power down Wake up sources P89LPC907 P89LPC908 Wakeup if in Power down EA IE0 7 Interrupt to CPU BOPD EBO KBIF EKBI EC WDOVF EWDRT TF0 ET0 TF1 ET1 CMF ERTC RTCCON 1 RTCF Wakeup if in Power down EA IE0 7 Interrupt to CPU BOPD EBO KBIF EKBI EC WDOVF EWDRT TF0 ET0 TF1 ET1 CMF TI RI RI ES ESR TI EST ERTC RTCCON 1 RTCF ...

Page 34: ...Philips Semiconductors User s Manual Preliminary P89LPC906 907 908 INTERRUPTS 2003 Dec 8 34 ...

Page 35: ...l output that serve different purposes One of these pullups called the very weak pullup is turned on whenever the port latch for the pin contains a logic 1 This very weak pullup sources a very small current that will pull the pin high if it is left floating A second pullup called the weak pullup is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1...

Page 36: ...mitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC906 907 908 datasheet AC Characteristics for glitch filter specifications Figure 4 1 Quasi Bidirectional Output OPEN DRAIN OUTPUT CONFIGURATION The open drain output configuration turns off all pullups and only drives the pulldown transistor of the port pin when the port latch contains a logic 0 To be used as...

Page 37: ...nfiguration is shown in Figure 4 4 A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit please refer to the P89LPC906 907 908 datasheet AC Characteristics for glitch filter specifications Figure 4 4 Push Pull Output PORT 0 ANALOG FUNCTIONS The P89LPC906 907 908 incorporates an analog comparator In order to give the best analog performance and minimize power...

Page 38: ...6 CMP1 P1 5 not configurable RST Input only Usage as general purpose input or RST is determined by User Configuration Bit RPD UCFG1 6 Always a reset input during a power on sequence P3 0 P3M1 0 P3M2 0 XTAL2 CLKOUT P3 1 P3M1 1 P3M2 1 XTAL1 Port Pin Configuration SFR Bits Alternate Usage Notes PxM1 y PxM2 y P0 4 P0M1 4 P0M2 4 KBI4 CIN1A Refer to section Port 0 Analog Functions for usage as analog in...

Page 39: ...9LPC906 907 908 I O PORTS 2003 Dec 8 39 All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times ...

Page 40: ...Philips Semiconductors User s Manual Preliminary P89LPC906 907 908 I O PORTS 2003 Dec 8 40 ...

Page 41: ...ld be held for at least one full machine cycle The Timer or Counter function is selected by control bit T0C T in the Special Function Register TMOD Timer 0 and Timer 1 of the P89LPC906 and P89LPC908 and Timer 1 of the P89LPC907 have four operating modes modes 0 1 2 and 3 which are selected by bit pairs TnM1 TnM0 in TMOD Modes 0 1 2 and 3 are the same for both Timers Mode 3 is different The operati...

Page 42: ...hown in Figure 5 6 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 TAMOD P89LPC907 Address 8Fh Not bit addressable Reset Source s Any reset Reset Value xxx0xxx0B BIT SYMBOL FUNCTION TAMOD 7 1 Reserved for future use Should not be set to 1 by user p...

Page 43: ...nd 254 and The high period of the TF0 is always 256 TH0 Loading TH0 with 00h will force the T0 pin high loading TH0 with FFh will force the T0 pin low Note that an interrupt can still be enabled on the low to high transition of TF0 and that TF0 can still be cleared in software as in any other modes Figure 5 3 Timer Counter Control register TCON TCON Address 88h Bit addressable Reset Source s Any r...

Page 44: ...load TLn 5 bits TRn T0 Pin T0C T 0 T0C T 1 THn 8 bits Interrupt T0 Pin Control Toggle ENT0 AUXR1 4 TFn PCLK Overflow T0 Pin functions available on P89LPC907 TLn 8 bits TRn T0 Pin T0C T 0 T0C T 1 THn 8 bits Interrupt T0 Pin Control Toggle ENT0 AUXR1 4 TFn PCLK Overflow T0 Pin functions available on P89LPC907 TLn 8 bits TRn T0 Pin T0C T 0 T0C T 1 THn 8 bits Interrupt T0 Pin Control Toggle ENT0 AUXR1...

Page 45: ... bit ENT0 in the AUXR1 register The port output will be a logic 1 prior to the first timer overflow when this mode is turned on In order for this mode to function the T0C T bit must be cleared selecting PCLK as the clock source for the timer TL0 8 bits TR0 T0 Pin C T 0 C T 1 Interrupt T0 Pin Control Toggle ENT0 TF0 PCLK Overflow TH0 8 bits Interrupt Control TF1 Overflow TR1 PCLK T0 Pin functions a...

Page 46: ...Philips Semiconductors User s Manual Preliminary P89LPC906 907 908 TIMERS 0 AND 1 2003 Dec 8 46 ...

Page 47: ...RTC will use either the XTAL1 2 oscillator s output or CCLK as its clock source The possible clocking combinations are shown in Table below There are three SFRs used for the RTC RTCCON Real time clock control RTCH Real time clock counter reload high bits 22 15 RTCL Real time clock counter reload low bits 14 7 The Real time clock system timer can be enabled by setting the RTCEN RTCCON 0 bit The Rea...

Page 48: ...y crystal XCLK 01 10 11 High frequency crystal DIVM CCLK 0 0 1 00 Medium frequency crystal DIVM Medium frequency crystal XCLK 01 10 11 Medium frequency crystal DIVM CCLK 0 1 0 00 Low frequency crystal DIVM Low frequency crystal XCLK 01 10 11 Low frequency crystal DIVM CCLK 23 bit down counter 7 bit prescaler RTCH RTCL Interrupt if enabled shared w WDT Power On Reset Low freq Med freq High freq CCL...

Page 49: ...K 1 0 0 00 WDT Oscillator DIVM High frequency crystal XCLK 01 Medium frequency crystal XCLK 10 Low frequency crystal XCLK 11 WDT Oscillator DIVM CCLK 1 0 1 xx undefined 1 1 0 1 1 1 00 external clock DIVM external clock XCLK 01 10 11 external clock DIVM CCLK FOSC2 UCFG1 2 FOSC1 UCFG1 1 FOSC0 UCFG1 0 RTCS1 0 CCLK Frequency RTC Clock Frequency 0 0 0 x undefined 0 0 1 0 1 0 0 1 1 00 RC Oscillator DIVM...

Page 50: ...E CLOCK INTERRUPT WAKE UP If ERTC RTCCON 1 EWDRT IEN0 6 and EA IEN0 7 are set to 1 RTCF can be used as an interrupt source This interrupt vector is shared with the watchdog timer It can also be a source to wake up the device RESET SOURCES AFFECTING THE REAL TIME CLOCK Only power on reset will reset the Real time Clock and its associated SFRs to their default state 1 0 0 00 WDT Oscillator DIVM unde...

Page 51: ...ed for future use Should not be set to 1 by user programs RTCCON 1 ERTC Real time Clock interrupt enable The Real time clock shares the same interrupt as the watchdog timer Note that if the user configuration bit WDTE UCFG1 7 is 0 the watchdog timer can be enabled to generate an interrupt Users can read the RTCF RTCCON 7 bit to determine whether the Real time clock caused the interrupt RTCCON 0 RT...

Page 52: ...Philips Semiconductors User s Manual Preliminary P89LPC906 907 908 REAL TIME CLOCK SYSTEM TIMER 2003 Dec 8 52 ...

Page 53: ...ode If PMOD1 0 11 the circuitry for the Brownout Detection is disabled for lowest power consumption BOPD defaults to 0 indicating brownout detection is enabled on power on if BOE is programmed If Brownout Detection is enabled the operating voltage range for VDD is 2 7V 3 6V and the brownout condition occurs when VDD falls below the Brownout trip voltage VBO see D C Electrical Characteristics and i...

Page 54: ... 4 EBO IEN0 5 EA IEN0 7 Description 0 erased XX X X X X Brownout disabled VDD operating range is 2 4V 3 6V 1 programmed 11 total power down X X X X 11 any mode other than total power down 1 brownout detect powered down X X X Brownout disabled VDD operating range is 2 4V 3 6V However BOPD is default to 0 upon power up 0 brownout detect active 0 brownout detect generates reset X X Brownout reset ena...

Page 55: ...immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 1024 CPU clocks after start up when one of the crystal oscillator configurations is used or 256 clocks after start up for the internal RC or external clock input configurations Some chip functions continue to operate and draw power during Power down mode increasing the total power used duri...

Page 56: ...ng error status FE for the UART This bit also determines the location of the UART receiver interrupt RI see description on RI in Figure 8 3 PCON 5 BOPD Brownout Detect Power down When 1 Brownout Detect is powered down and therefore disabled When 0 Brownout Detect is enabled Note BOPD must be 0 before any programming or erasing commands can be issued Otherwise these commands will be aborted PCON 4 ...

Page 57: ...re use PCONA 5 VCPD Analog Voltage Comparator Power down When 1 the voltage comparator is powered down User must disable the voltage comparator prior to setting this bit PCONA 4 Not used Reserved for future use PCONA 3 Not used Reserved for future use PCONA 2 Not used Reserved for future use PCONA 1 SPD Serial Port UART Power down When 1 the internal clock to the UART is disabled Note that in eith...

Page 58: ...Philips Semiconductors User s Manual Preliminary P89LPC906 907 908 POWER MONITORING FUNCTIONS 2003 Dec 8 58 ...

Page 59: ...RxD a start bit logical 0 8 data bits LSB first and a stop bit logical 1 When data is received the stop bit is stored in RB8 in Special Function Register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Baud Rate Generator and Selection section MODE 2 11 bits are transmitted through TxD or received through RxD start bit logical 0 8 data b...

Page 60: ...nerator is disabled the BRGEN bit in the BRGCON register is 0 This avoids the loading of an interim value to the baud rate generator CAUTION If either BRGR0 or BRGR1 is written when BRGEN 1 the result is unpredictable Table 8 2 Baud Rate Generation for UART Register Description SFR Location PCON Power Control 87H SCON Serial Port UART Control 98H SBUF Serial Port UART Data Buffer 99H SADDR Serial ...

Page 61: ... condition has been detected the UART will go into an idle state and remain in this idle state until a stop bit has been received The break detect can be used to reset the device by setting the EBRR bit AUXR1 6 A break detect reset will force the high byte of the program counter to be equal to the Boot Vector contents and the low byte cleared to 00h The first instruction will be fetched from this ...

Page 62: ... the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then Rl will not be activated if the received 9th data bit RB8 is 0 In Mode 0 SM2 should be 0 In Mode 1 SM2 must be 0 SCON 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception SCON 3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3 Set or c...

Page 63: ...e number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to SBUF and there is also one more transmit interrupt generated at the beginning INTLO 0 or the end INTLO 1 of the STOP bit of the last character sent i e no more data in buffer This last interrupt can be used to indicate that all transmit operations are ...

Page 64: ...t bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is lost If bo...

Page 65: ...d when 11 consecutive bits are sensed low and is reported in the status register SSTAT For Mode 1 this consists of the start bit 8 data bits and two stop bit times For Modes 2 3 this consists of the start bit 9 data bits and one stop bit The break detect bit is cleared in software or by a reset The break detect can be used to reset the device This occurs if the UART is enabled and the the EBRR bit...

Page 66: ...The following occurs during a transmission assuming eight data bits 1 The double buffer is empty initially 2 The CPU writes to SBUF 3 The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately 4 If there is more data go to 6 else continue on 5 5 If there is no more data then If DBISEL is 0 no more interrupts will occur If DBISEL is 1 and INTLO is 0 a Tx interrupt wil...

Page 67: ...2 and 3 becomes as follows 1 The double buffer is empty initially 2 The CPU writes to TB8 3 The CPU writes to SBUF 4 The SBUF TB8 data is loaded to the shift register and a Tx interrupt is generated immediately 5 If there is more data go to 7 else continue on 6 6 If there is no more data then If DBISEL is 0 no more interrupt will occur If DBISEL is 1 and INTLO is 0 a Tx interrupt will occur at the...

Page 68: ...the data bytes that follow The slaves that weren t being addressed leave their SM2 bits set and go on about their business ignoring the subsequent data bytes Note that SM2 has no effect in Mode 0 and must be 0 in Mode 1 AUTOMATIC ADDRESS RECOGNITION Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the...

Page 69: ...the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for eac...

Page 70: ...Philips Semiconductors User s Manual Preliminary P89LPC906 907 908 UART 2003 Dec 8 70 ...

Page 71: ...rownout Detect Watchdog Timer Software reset UART break character detect reset P89LPC908 For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a 0 to the corresponding bit More than one flag bit may be set During a power on reset both POF and BOF are set but...

Page 72: ...p condition The POF flag will remain set until cleared by software by writing a 0 to the bit Note On a Power on reset both BOF and this bit will be set while the other flag bits are cleared RSTSRC 3 R_BK Break detect reset If a break detect occurs and EBRR AUXR1 6 is set to 1 a system reset will occur This bit is set to indicate that the system reset is caused by a break detect Cleared by software...

Page 73: ...CONFIGURATION The comparator control register CMP1 is shown in Figure 10 1 The possible configurations for the comparator are shown in Figure 10 3 Figure 10 1 Comparator Control Register CMP1 CMP1 Address ACh Not bit addressable Reset Source s Any reset Reset Value xx000000B BIT SYMBOL FUNCTION CMP 7 6 Reserved for future use CMP 5 CE1 Comparator enable When set the comparator function is enabled ...

Page 74: ...r s output COx goes high If the comparator output was low and then is disabled the resulting transition of the comparator output from a low to high state will set the the comparator flag CMFx This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparat...

Page 75: ...FIGURATION EXAMPLE The code shown below is an example of initializing the comparator This comparator is configured to use the CMPREF inputs The comparator output drives the CMP pin and generates an interrupt when the comparator output changes CMPINIT MOV PT0AD 030h Disable digital INPUTS on pins that are used for analog functions CIN CMPREF ANL P0M2 0CFh Disable digital OUTPUTS on pins that are us...

Page 76: ...Philips Semiconductors User s Manual Preliminary P89LPC906 907 908 ANALOG COMPARATORS 2003 Dec 8 76 ...

Page 77: ...er needs to set KBPATN 0FFH and PATN_SEL 0 not equal then any key connected to Port0 which is enabled by KBMASK register will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumpti...

Page 78: ...Reserved KBMASK 6 When set enables P0 6 as a cause of a Keypad Interrupt KBMASK 5 When set enables P0 5 as a cause of a Keypad Interrupt KBMASK 4 When set enables P0 4 as a cause of a Keypad Interrupt KBMASK 3 0 Reserved Note the Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective Bits positions KBMASK 7 KBMASK 3 KBMASK 2 KBMASK 1 and KBMASK 0 should a...

Page 79: ...along with WDTE is designed to force certain operating conditions at power up Refer to the Table for details Table 12 1 Watchdog timer configuration Figure 12 3 shows the watchdog timer in watchdog mode It consists of a programmable 13 bit prescaler and an 8 bit down counter The down counter is clocked decremented by a tap taken from the prescaler The clock source for the prescaler is either PCLK ...

Page 80: ...V WFEED1 0A5h do watchdog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt This sequence assumes that the P89LPC906 907 908 interrupt system is enabled and there is a possibility of an interrupt request occuring during the feed sequence If an interrupt was allowed to be serviced and the service routine contained any SFR writes it would trigger a watchdog reset If it is ...

Page 81: ...le Reset Source s See reset value below Reset Value 111xx1 1B Note WDCON 7 6 5 2 0 set to 1 any reset WDCON 1 cleared to 0 on Power on reset set to 1 on watchdog reset not affected by any other reset BIT SYMBOL FUNCTION WDCON 7 5 PRE2 PRE0 Clock Prescaler Tap Select Refer to Table for details WDCON 4 3 Reserved for future use Should not be set to 1 by user program WDCON 2 WDRUN Watchdog Run Contro...

Page 82: ...or Clock Nominal 12MHz CCLK 6MHz CCLK 2 Watchdog Clock 000 0 33 82 5µs 5 50µs 255 8 193 20 5ms 1 37ms 001 0 65 162 5µs 10 8µs 255 16 385 41 0ms 2 73ms 010 0 129 322 5µs 21 5µs 255 32 769 81 9ms 5 46ms 011 0 257 642 5µs 42 8µs 255 65 537 163 8ms 10 9ms 100 0 513 1 28ms 85 5µs 255 131 073 327 7ms 21 8ms 101 0 1 025 2 56ms 170 8µs 255 262 145 655 4ms 43 7ms 110 0 2 049 5 12ms 341 5µs 255 524 289 1 31...

Page 83: ...TOF is cleared by writing a 0 to this bit in software When an underflow occurs the contents of WDL is reloaded into the down counter and the watchdog timer immediately begins to count down again A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs Incorrect feeds are ignored in this mode 8 Bit Down Counter MOV WFEED1 0A5H MOV WFEED2 05AH WDL C1H PRE2 PRE1 ...

Page 84: ...n in Figure 12 3 the selection is loaded after a watchdog feed sequence In addition due to clock synchronization logic it can take two old clock cycles before the old clock source is deselected and then an additional two new clock cycles before the new clock source is selected Since the prescaler starts counting immediately after a feed switching clocks can cause some inaccuracy in the prescaler c...

Page 85: ...required in order to have a periodic wakeup is determined by the power consumption of the internal oscillator source used to produce the wakeup The Real time clock running from the internal RC oscillator can be used The power consumption of this oscillator is approximately 300uA Instead if the WDT is used to generate interrupts the current is reduced to approximately 50uA Whenever the WDT underflo...

Page 86: ...Philips Semiconductors User s Manual Preliminary P89LPC906 907 908 WATCHDOG TIMER 2003 Dec 8 86 ...

Page 87: ...s the DPS bit is toggled Specific instructions affected by the Data Pointer selection are INC DPTR Increments the Data Pointer by 1 JMP A DPTR Jump indirect relative to DPTR value AUXR1 Address A2h Not bit addressable Reset Source s Any reset Reset Value 000000x0B BIT SYMBOL FUNCTION AUXR1 7 CLKLP Clock Low Power Select When set reduces power consumption in the clock circuits Can be used when the ...

Page 88: ... that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC906 907 908 since the part does not have an external data bus However they may be used to access Flash configuration information see Flash Configuration section Bit 2 of AUXR1 is permanently wired as a...

Page 89: ...nstruction and thus is suitable for use as non volatile data stor age In addition the user s code may access additional flash elements These include UCFG1 the Boot Vector Status Bit secu rity bytes and signature bytes Access of these elements uses a slightly different method than that used to access the user code memory USING FLASH AS DATA STORAGE IAP Lite provides an erase program function that m...

Page 90: ...de should check the OI flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user s code will need to repeat the process starting with loading the page register The erase program cycle takes 4ms to complete regardless of the number of bytes that were loaded into the page register Erasing programming of a single byte or multiple byt...

Page 91: ...sector or page FMCON 0 OI Operation interrupted Set when cycle aborted due to an interrupt or reset 7 6 5 4 3 2 1 0 HVA HVE SV OI Inputs R3 number of bytes to program byte R4 page address MSB byte R5 page address LSB byte R7 pointer to data buffer in RAM byte Outputs R7 status byte C clear on no error set on error LOAD EQU 00H EP EQU 68H PGM_USER MOV FMCON LOAD load command clears page register MO...

Page 92: ... Control Register When read this is the status register When written this is a command register Note that the status bits are cleared to 0 s when the command is written FMDATA Flash Data Register Accepts data to be loaded into or from the flash element FMADRL Flash memory address low Used to specify the flash element The flash elements that may be accessed and their addresses are shown in Table 14...

Page 93: ...s during erasing programming the user code should check the OI flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user s code will need to repeat the process READING ADDITIONAL FLASH ELEMENTS The read cycle is accomplished using the following steps Write the address of the flash element to FMADRL Write the CONF command 6CH to FM...

Page 94: ... for return MOV A R7 read status ANL A 0FH save only four lower bits JNZ BAD see if good or bad CLR C clear error flag if good RET and return BAD SETB C set error flag if bad RET and return unsigned char Fm_stat status result bit PGM_EL unsigned char unsigned char bit prog_fail void main prog_fail PGM_EL 0x02 0x1C bit PGM_EL unsigned char el_addr unsigned char el_data define CONF 0x6C access flash...

Page 95: ... REG921 H unsigned char READ_EL unsigned char unsigned char GET_EL void main GET_EL READ_EL 0x02 unsigned char READ_EL unsigned char el_addr define CONF 0x6C access flash elements unsigned char el_data local for element data FMADRL el_addr write element address to addr reg FMCON CONF access flash elements command el_data FMDATA read the element data return el_data ...

Page 96: ... selection defined by RPE bit Other sources of reset will not override the RPE bit UCFG1 5 BOE Brownout Detect Enable see section Brownout Detection on page 53 UCFG1 4 WDSE Watchdog Safety Enable bit Refer to Table for details UCFG1 3 Reserved should remain unprogrammed at zero UCFG1 2 0 FOSC2 FSOC0 CPU oscillator type select See section Low Power Select P89LPC906 on page 28 for additional informa...

Page 97: ...bal erase are allowed 1 x x Security violation flag set for program or erase commands Cycle aborted Memory contents unchanged Global erase is allowed SECx Address xxxxh Unprogrammed value 00h BIT SYMBOL FUNCTION SECx 7 3 Reserved should remain unprogrammed at zero SECx 2 EDISx Erase Disable x Disables the ability to perform an erase of sector x in IAP mode When programmed this bit and sector x can...

Page 98: ...start execution at an address comprised of 00H in the lower eight bits and this BOOTVEC as the upper bits after a reset See section Power On reset code execution on page 71 7 6 5 4 3 2 1 0 BOOTV4 BOOTV3 BOOTV2 BOOTV1 BOOTV0 BOOTSTAT Address xxxxh Factory default value 00h BIT SYMBOL FUNCTION BOOTSTAT 7 1 Reserved should remain unprogrammed at zero BOOTSTAT 0 BSB Boot Status Bit If programmed to 1 ...

Page 99: ...egister from A with borrow 1 1 98 9F SUBB A dir Subtract direct byte from A with borrow 2 1 95 SUBB A Ri Subtract indirect memory from A with borrow 1 1 96 97 SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 07 DEC A Decrement A 1 1 14 DEC Rn Decrement r...

Page 100: ... direct byte 2 1 62 XRL dir data Exclusive OR immediate to direct byte 3 2 63 CLR A Clear A 1 1 E4 CPL A Complement A 1 1 F4 SWAP A Swap Nibbles of A 1 1 C4 RL A Rotate A left 1 1 23 RLC A Rotate A left through carry 1 1 33 RR A Rotate A right 1 1 03 RRC A Rotate A right through carry 1 1 13 DATA TRANSFER MOV A Rn Move register to A 1 1 E8 EF MOV A dir Move direct byte to A 2 1 E5 MOV A Ri Move in...

Page 101: ...ta A16 1 2 F0 PUSH dir Push direct byte onto stack 2 2 C0 POP dir Pop direct byte from stack 2 2 D0 XCH A Rn Exchange A and register 1 1 C8 CF XCH A dir Exchange A and direct byte 2 1 C5 XCH A Ri Exchange A and indirect memory 1 1 C6 C7 XCHD A Ri Exchange A and indirect memory nibble 1 1 D6 D7 BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 ...

Page 102: ...bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 10 JMP A DPTR Jump indirect relative DPTR 1 2 73 JZ rel Jump on accumulator 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relat...

Page 103: ...Philips Semiconductors User s Manual Preliminary P89LPC906 907 908 REVISION HISTORY 2003 Dec 8 103 16 REVISION HISTORY 2003 Dec 8 Initial release ...

Page 104: ...Philips Semiconductors User s Manual Preliminary P89LPC906 907 908 REVISION HISTORY 2003 Dec 8 104 ...

Page 105: ...ce voltage 79 interrupt 74 power reduction modes 74 Analog comparators and power reduction 37 B Block diagram 9 BRGCON writing to 23 Brownout detection 53 enabling and disabling 53 operating range 53 options 54 rise and fall times of Vdd 53 C CLKLP 28 Clock CPU clock 25 CPU divider DIVM 28 29 definitions 25 external input option 27 PCLK 25 RCCLK 25 wakeup delay 27 Clock output 26 D Data EEPROM ...

Page 106: ... 41 47 53 59 71 73 77 79 87 89 99 103 Boot Status 98 Boot Vector 98 features 89 hardware activation of the boot loader 71 power on reset code execution 71 I IAP programming 89 Interrupts 35 arbitration ranking 31 external input pin glitch suppression 32 external inputs 31 keypad 32 priority structure 31 wake up from power down 32 Interrutps edge triggered 32 ISP programming 89 K Keypad interrupt K...

Page 107: ...s additional features 38 I O 35 input only configuration 37 open drain output configuration 36 Port 0 analog functions 37 Port 2 in 20 pin package 37 push pull output configuration 37 quasi bidirectional output configuration 35 Power monitoring functions 71 Power reduction modes 54 normal mode 55 power down mode partial 55 Power down mode total 55 Power on detection 54 R Real time clock 47 clock s...

Page 108: ... 63 TAMOD 42 TCON 43 TMOD 41 TRIM 26 27 91 UCFG1 96 WDCON 81 SFRs undefined locations use of 15 Special Function Registers SFR table 15 18 21 T Timer counters 41 mode 0 42 mode 1 42 mode 2 8 bit auto reload 42 mode 3 seperates TL0 TH0 43 mode 6 8 bit PWM 43 toggle output 45 TRIM SFR power on reset value 23 U UART 59 automatic address recognition 68 baud rate generator 60 BRGR1 and BRGR0 updating 6...

Page 109: ...shift register 59 mode 1 64 mode 1 8 bit variable baud rate 59 mode 2 65 mode 2 9 bit fixed baud rate 59 mode 3 65 mode 3 9 bit variable baud rate 59 multiprocessor communications 68 status register 63 transmit interrupts with double buffering enabled modes 1 2 and 3 66 W Watchdog timer 79 feed sequence 80 timer mode 83 watchdog function 79 watchdog timeout values 82 WDCLK 0 and CPU power down 84 ...

Page 110: ...tems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes in th...

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