Philips P89LPC901 User Manual Download Page 113

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Philips Semiconductors

P89LPC901/902/903

INDEX

User’s Manual - Preliminary -

2003 Dec 8

113

double buffering in 9-bit mode

double buffering in different modes

framing error

63, 67

mode 0

mode 0 (shift register)

mode 1

mode 1 (8-bit variable baud rate)

mode 2

mode 2 (9-bit fixed baud rate)

mode 3

mode 3 (9-bit variable baud rate)

multiprocessor communications

SFR locations.

status register

transmit interrupts with double buffering enabled (modes 1, 2 and 3)

Watchdog timer

feed sequence

timer mode

watchdog function

watchdog timeout values

WDCLK = 0 and CPU power down

Summary of Contents for P89LPC901

Page 1: ...EGRATED CIRCUITS Philips Semiconductors PHILIPS 2003 Dec 8 P89LPC901 902 903 8 bit microcontrollers with accelerated two clock 80C51 core 1KB 3V Low Power byte eraseable Flash with 128 Byte RAM USER MANUAL ...

Page 2: ... 27 Medium Speed Oscillator Option P89LPC901 27 High Speed Oscillator Option P89LPC901 27 Oscillator Option Selection P89LPC901 28 Clock Output P89LPC901 28 On Chip RC oscillator Option 28 Watchdog Oscillator Option 29 External Clock Input Option P89LPC901 29 CPU Clock CCLK Wakeup Delay 32 CPU Clock CCLK Modification DIVM Register 32 Low Power Select P89LPC901 33 3 Interrupts 35 Interrupt Priority...

Page 3: ...R1 and BRGR0 SFRs 62 Framing Error 63 Break Detect 63 More About UART Mode 0 65 More About UART Mode 1 66 More About UART Modes 2 and 3 67 Framing Error and RI in Modes 2 and 3 with SM2 1 67 Break Detect 67 Double Buffering 68 Double Buffering in Different Modes 68 Transmit Interrupts with Double Buffering Enabled Modes 1 2 and 3 68 The 9th Bit Bit 8 in Double Buffering Modes 1 2 and 3 69 Multipro...

Page 4: ...r 89 13 Additional Features 91 Software Reset 91 Dual Data Pointers 91 14 Flash program memory 93 General description 93 Features 93 Introduction to IAP Lite 93 Using Flash as data storage 93 Accessing additional flash elements 96 Erase programming additional flash elements 97 Reading additional flash elements 97 User Configuration Bytes 99 User Security Bytes 101 Boot Vector 102 Boot Status 102 1...

Page 5: ...t 40 Open Drain Output 40 Input Only 41 Push Pull Output 41 Port Output Configuration P89LPC901 42 Port Output Configuration P89LPC902 42 Port Output Configuration P89LPC903 42 Timer Counter Mode Control register TMOD 45 Timer Counter Auxiliary Mode Control register TAMOD 46 Timer Counter Control register TCON 47 Timer Counter 0 or 1 in Mode 0 13 bit counter 48 Timer Counter 0 or 1 in Mode 1 16 bi...

Page 6: ...ttern Register P89LPC903 80 Keypad Control Register 80 Keypad Interrupt Mask Register KBM P89LPC901 80 Keypad Interrupt Mask Register KBM P89LPC902 81 Keypad Interrupt Mask Register KBM P89LPC903 81 Watchdog timer configuration 83 Watchdog Prescaler 84 Watchdog Timer Control Register 85 P89LPC901 902 903 Watchdog Timeout Values 86 Watchdog Timer in Watchdog Mode WDTE 1 86 Watchdog Timer in Timer M...

Page 7: ...utes instructions six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC901 902 903 in order to reduce component count board space and system cost Pin Configurations 8 Pin Packages CLKOUT XTAL2 P3 0 1 2 3 4 8 7 6 5 RST P1 5 VSS VDD XTAL1 P3 1 P1 2 T0 P0 5 CMPREF KBI5 P0 4 CIN1A KBI4 P89LPC901 1 2 3 4 8 7 6 5 RST P1 5 VSS VDD P0 2 CIN2A KBI2 ...

Page 8: ...Ext crystal pins X2 clkout T0 PWM output CMP1 input CMP2 input CMP Ref Input CMP1 CMP2 outputs UART TxD RxD P89LPC901 Y Y Y Y Y P89LPC902 Y Y Y Y P89LPC903 Y Y Y Y Y VDD VSS PORT1 PORT0 P89 LPC901 CIN1A CMPREF KBI4 KBI5 CLKOUT XTAL1 RST XTAL2 PORT3 T0 VDD VSS PORT1 PORT0 P89 LPC902 CIN1A CMPREF CIN2A CMP2 KBI4 KBI5 KBI6 KBI0 RST CMP1 KBI2 VDD VSS PORT1 PORT0 P89 LPC903 CIN1A CMPREF KBI4 KBI5 KBI2 ...

Page 9: ... Flash Internal Bus Timer0 Timer1 Keypad Interrupt Power Monitor Power On Reset Brownout Reset Configurable Oscillator Crystal or Resonator On Chip RC Oscillator Programmable Oscillator Divider CPU Clock Port 3 Configurable I Os Watchdog Timer and Oscillator Analog Comparator Real Time Clock System Timer High Performance Accelerated 2 clock 80C51 CPU Port 1 Configurable I Os ...

Page 10: ...figurable I Os 128 byte Data RAM 1KB Code Flash Internal Bus Timer0 Timer1 Keypad Interrupt Power Monitor Power On Reset Brownout Reset On Chip RC Oscillator Programmable Oscillator Divider CPU Clock Port 1 Input Watchdog Timer and Oscillator Analog Comparators Real Time Clock System Timer High Performance Accelerated 2 clock 80C51 CPU ...

Page 11: ...urable I Os 128 byte Data RAM 1KB Code Flash Internal Bus Timer0 Timer1 Keypad Interrupt Power Monitor Power On Reset Brownout Reset On Chip RC Oscillator Programmable Oscillator Divider CPU Clock Port 1 Input Watchdog Timer and Oscillator UART Analog Comparators Real Time Clock System Timer High Performance Accelerated 2 clock 80C51 CPU ...

Page 12: ...nd outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to the section on I O port configuration and the DC Electrical Characteristics in the Data Sheet for details P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below 5 I O P1 2 Port 1 bit 2 I O T0 Timer coun...

Page 13: ...when XTAL1 XTAL2 are used to generate clock source for the Real Time clock system timer 2 I O P3 1 Port 3 bit 1 I XTAL1 Input to the oscillator circuit and internal clock generator circuits when selected via the FLASH configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source AND if XTAL1 XTAL2 are not used to generate the clock for the Real...

Page 14: ... Input 0 2 I O P0 2 Port 0 bit 2 I CIN2A Comparator 2 positive input I KBI2 Keyboard Input 2 7 I O P0 4 Port 0 bit 4 I CIN1A Comparator 1 positive input I KBI4 Keyboard Input 4 6 I O P0 5 Port 0 bit 5 I CMPREFComparator reference negative input I KBI5 Keyboard Input 5 5 I O P0 6 Port 0 bit 6 O CMP1 Comparator 1 output I KBI6 Keyboard Input 6 P1 5 4 I Port 1 Port 1 is a single bit input only port I...

Page 15: ... 5 P1 0 P1 5 3 4 5 Port 1 Port 1 is an I O port with a user configurable output types During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to the section on I O port con...

Page 16: ...d Addresses Reset Value MSB LSB Hex Binary E7 E6 E5 E4 E3 E2 E1 E0 ACC Accumulator E0H 00H 00000000 AUXR1 Auxiliary Function Register A2H CLKLP ENT0 SRST 0 DPS 00H1 000000x0 F7 F6 F5 F4 F3 F2 F1 F0 B B Register F0H 00H 00000000 CMP1 Comparator 1 Control Register ACH CE1 CN1 CO1 CMF1 00H1 xx000000 DIVM CPU Clock Divide by M Control 95H 00H 00000000 DPTR Data Pointer 2 bytes DPH Data Pointer High 83...

Page 17: ...000000 P1M1 Port 1 Output Mode 1 91H P1M1 5 P1M1 2 FFH1 11111111 P1M2 Port 1 Output Mode 2 92H P1M2 5 P1M2 2 00H1 00000000 P3M1 Port 3 Output Mode 1 B1H P3M1 1 P3M1 0 03H1 xxxxxx11 P3M2 Port 3 Output Mode 2 B2H P3M2 1 P3M2 0 00H1 xxxxxx00 PCON Power Control Register 87H BOPD BOI GF1 GF0 PMOD1 PMOD0 00H 00000000 PCONA Power Control Register A B5H RTCPD VCPD 00H1 00000000 D7 D6 D5 D4 D3 D2 D1 D0 PSW...

Page 18: ...AH 00H 00000000 TL1 Timer 1 Low 8BH 00H 00000000 TMOD Timer 0 and 1 Mode 89H T1M1 T1M0 T0C T T0M1 T0M0 00H 00000000 TRIM Internal Oscillator Trim Register 96H ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM 0 Notes 4 5 WDCON Watchdog Control Register A7H PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK Notes 3 5 WDL Watchdog Load C1H FFH 11111111 WFEED1 Watchdog Feed 1 C2H WFEED2 Watchdog Feed 2 C3H Name Descriptio...

Page 19: ...w 82H 00H 00000000 FMADRH Program Flash Address High E7H 00H 00000000 FMADRL Program Flash Address Low E6H 00H 00000000 FMCON Program Flash Control Read E4H BUSY HVA HVE SV OI 70H 01110000 Program Flash Control Write FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD 0 FMDATA Program Flash Data E5H 00H 00000000 AF AE AD AC AB AA A9 A8 IEN0 Interrupt Enable 0 A8H EA EWDRT EBO ET1 ET0 00H...

Page 20: ... D4 D3 D2 D1 D0 PSW Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P 00H 00000000 PT0AD Port 0 Digital Input Disable F6H PT0AD 5 PT0AD 4 PT0AD 2 00H xx00000x RSTSRC Reset Source Register DFH BOF POF R_WD R_SF R_EX Note 2 RTCCON Real Time Clock Control D1H RTCF RTCS1 RTCS0 ERTC RTCEN 60H1 5 011xxx00 RTCH Real Time Clock Register High D2H 00H5 00000000 RTCL Real Time Clock Register Low D3H 00H5 0000...

Page 21: ...SCRIPTION 2003 Dec 8 21 WDCON Watchdog Control Register A7H PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK Notes 3 5 WDL Watchdog Load C1H FFH 11111111 WFEED1 Watchdog Feed 1 C2H WFEED2 Watchdog Feed 2 C3H Name Description SFR Address Bit Functions and Addresses Reset Value MSB LSB Hex Binary ...

Page 22: ... CMF2 00H1 xx000000 DIVM CPU Clock Divide by M Control 95H 00H 00000000 DPTR Data Pointer 2 bytes DPH Data Pointer High 83H 00H 00000000 DPL Data Pointer Low 82H 00H 00000000 FMADRH Program Flash Address High E7H 00H 00000000 FMADRL Program Flash Address Low E6H 00H 00000000 FMCON Program Flash Control Read E4H BUSY HVA HVE SV OI 70H 01110000 Program Flash Control Write FMCMD 7 FMCMD 6 FMCMD 5 FMC...

Page 23: ...ister A B5H RTCPD VCPD SPD 00H1 00000000 D7 D6 D5 D4 D3 D2 D1 D0 PSW Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P 00H 00000000 PT0AD Port 0 Digital Input Disable F6H PT0AD 5 PT0AD 4 PT0AD 2 00H xx00000x RSTSRC Reset Source Register DFH BOF POF R_BK R_WD R_SF R_EX Note 2 RTCCON Real Time Clock Control D1H RTCF RTCS1 RTCS0 ERTC RTCEN 60H1 5 011xxx00 RTCH Real Time Clock Register High D2H 00H5 00...

Page 24: ... are cleared except POF and BOF the power on reset value is xx110000 3 After reset the value is 111001x1 i e PRE2 PRE0 are all 1 WDRUN 1 and WDCLK 1 WDTOF bit is 1 after watchdog reset and is 0 after power on reset Other resets will not affect WDTOF 4 On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 5 T...

Page 25: ...addressing using instructions other than MOVX and MOVC SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing CODE 1KB of Code memory accessed as part of program execution and via the MOVC instruction 1 KB Flash Code Memory Space 0000h 00FFh Sector 0 Sector 1 0100h 01FFh 0200h 02FFh Sector 2 Sector 3 0300h 03FFh Data ...

Page 26: ...Philips Semiconductors User s Manual Preliminary P89LPC901 902 903 GENERAL DESCRIPTION 2003 Dec 8 26 ...

Page 27: ...tions are configured when the FLASH is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 12 MHz The P89LPC902 and P89LPC903 devices allow the user to select between an on chip watchdog osci...

Page 28: ...prior to entering Idle saving additional power Note on reset the TRIM SFR is initialized with a factory preprogrammed value Therefore when setting or clearing the ENCLK bit the user should retain the contents of bits 5 0 of the TRIM register This can be done by reading the contents of the TRIM register into the ACC for example modifying bit 6 and writing this result back into the TRIM register Alt...

Page 29: ...a standard port pin or a clock output TRIM Address 96h Not bit addressable Reset Source s Power up only Reset Value On power up reset ENCLK 0 and TRIM 5 0 are loaded with the factory programmed value BIT SYMBOL FUNCTION TRIM 7 Reserved TRIM 6 ENCLK When ENCLK 1 CCLK 2 is output on the XTAL2 pin P3 0 provided that the crystal oscillator is not being used When ENCLK 0 no clock output is enabled P89L...

Page 30: ... 903 CLOCKS 2003 Dec 8 30 Figure 2 3 Block Diagram of Oscillator Control P89LPC901 RTC CPU High freq Med freq Low freq Watchdog Oscillator RC Oscillator XTAL1 XTAL2 2 DIVM WDT 7 3728MHz 400KHz CCLK PCLK Timer 0 1 OSC CLK Oscillator Clock CPU Clock FOSC2 0 RTCS1 0 ...

Page 31: ...minary P89LPC901 902 903 CLOCKS 2003 Dec 8 31 Figure 2 4 Block Diagram of Oscillator Control P89LPC902 RTC CPU Watchdog Oscillator RC Oscillator 2 DIVM WDT 7 3728MHz 400KHz CCLK PCLK Timer 0 1 OSC CLK Oscillator Clock CPU Clock FOSC2 0 RTCS1 0 ...

Page 32: ...ing the following formula CCLK frequency fOSC 2N Where fOSC is the frequency of OSCCLK N is the value of DIVM Since N ranges from 0 to 255 the CCLK frequency can be in the range of fOSC to fOSC 510 for N 0 CCLK fOSC This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events other tha...

Page 33: ...89LPC901 The P89LPC901 is designed to run at 12MHz CCLK maximum However if CCLK is 8MHz or slower the CLKLP SFR bit AUXR1 7 can be set to a 1 to lower the power consumption further On any reset CLKLP is 0 allowing highest performance This bit can then be set in software if CCLK is running at 8MHz or slower ...

Page 34: ...Philips Semiconductors User s Manual Preliminary P89LPC901 902 903 CLOCKS 2003 Dec 8 34 ...

Page 35: ...isters IP0 IP0H IP1 and IP1H An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are pending at the start of an instruction the request of higher priority level is se...

Page 36: ...1 Yes Watchdog Timer Real time Clock WDOVF RTCF 0053h EWDRT IEN0 6 IP0H 6 IP0 6 2 Yes KBI Interrupt KBIF 003Bh EKBI IEN1 1 IP1H 1 IP1 1 4 Yes Comparator interrupt CMF 0043h EC IEN1 2 IP1H 2 IP1 2 6 Yes Description Interrupt Flag Bit s Vector Address Interrupt Enable Bit s Interrupt Priority Arbitration Ranking Power down Wakeup Timer 0 Interrupt TF0 000Bh ET0 IEN0 1 IP0H 1 IP0 1 3 No Timer 1 Inter...

Page 37: ... cause the processor to wake up and resume operation Refer to the section on Power Reduction Modes for details External Interrupt Pin Glitch Suppression Most of the P89LPC901 902 903 pins have glitch suppression circuits to reject short glitches please refer to the P89LPC901 902 903 datasheet AC Electrical Characteristics for glitch filter specifications Figure 3 1 Interrupt sources enables and Po...

Page 38: ...es P89LPC902 Figure 3 3 Interrupt sources enables and Power down Wake up sources P89LPC903 Wakeup if in Power down EA IE0 7 Interrupt to CPU BOPD EBO KBIF EKBI EC WDOVF EWDRT TF0 ET0 TF1 ET1 CMF ERTC RTCCON 1 RTCF Wakeup if in Power down EA IE0 7 Interrupt to CPU BOPD EBO KBIF EKBI EC WDOVF EWDRT TF0 ET0 TF1 ET1 CMF TI RI RI ES ESR TI EST ERTC RTCCON 1 RTCF ...

Page 39: ...onal output that serve different purposes One of these pullups called the very weak pullup is turned on whenever the port latch for the pin contains a logic 1 This very weak pullup sources a very small current that will pull the pin high if it is left floating A second pullup called the weak pullup is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logi...

Page 40: ...mitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC901 902 903 datasheet AC Characteristics for glitch filter specifications Figure 4 1 Quasi Bidirectional Output Open Drain Output Configuration The open drain output configuration turns off all pullups and only drives the pulldown transistor of the port pin when the port latch contains a logic 0 To be used as...

Page 41: ...iguration is shown in Figure 4 4 A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC901 902 903 datasheet AC Characteristics for glitch filter specifications Figure 4 4 Push Pull Output Port 0 Analog Functions The P89LPC901 902 903 incorporates up to two analog comparators In order to give the best analog performance and minimize...

Page 42: ...configurable RST Input only Usage as general purpose input or RST is determined by User Configuration Bit RPD UCFG1 6 Always a reset input during a power on sequence P3 0 P3M1 0 P3M2 0 XTAL2 CLKOUT P3 1 P3M1 1 P3M2 1 XTAL1 Port Pin Configuration SFR Bits Alternate Usage Notes PxM1 y PxM2 y P0 0 P0M1 0 P0M2 0 KBI0 CMP2 Refer to section Port 0 Analog Functions for usage as analog inputs CINxA and CM...

Page 43: ...9LPC901 902 903 I O PORTS 2003 Dec 8 43 All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times ...

Page 44: ...Philips Semiconductors User s Manual Preliminary P89LPC901 902 903 I O PORTS 2003 Dec 8 44 ...

Page 45: ...ld be held for at least one full machine cycle The Timer or Counter function is selected by control bit T0C T in the Special Function Register TMOD Timer 0 and Timer 1 of the P89LPC902 and P89LPC903 and Timer 1 of the P89LPC901 have four operating modes modes 0 1 2 and 3 which are selected by bit pairs TnM1 TnM0 in TMOD Modes 0 1 2 and 3 are the same for both Timers Mode 3 is different The operati...

Page 46: ...hown in Figure 5 6 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 TAMOD P89LPC901 Address 8Fh Not bit addressable Reset Source s Any reset Reset Value xxx0xxx0B BIT SYMBOL FUNCTION TAMOD 7 1 Reserved for future use Should not be set to 1 by user p...

Page 47: ...254 and The high period of the TF0 is always 256 TH0 Loading TH0 with 00h will force the T0 pin high loading TH0 with FFh will force the T0 pin low Note that an interrupt can still be enabled on the low to high transition of TF0 and that TF0 can still be cleared in software as in any other modes Figure 5 3 Timer Counter Control register TCON TCON Address 88h Bit addressable Reset Source s Any rese...

Page 48: ...load TLn 5 bits TRn T0 Pin T0C T 0 T0C T 1 THn 8 bits Interrupt T0 Pin Control Toggle ENT0 AUXR1 4 TFn PCLK Overflow T0 Pin functions available on P89LPC901 TLn 8 bits TRn T0 Pin T0C T 0 T0C T 1 THn 8 bits Interrupt T0 Pin Control Toggle ENT0 AUXR1 4 TFn PCLK Overflow T0 Pin functions available on P89LPC901 TLn 8 bits TRn T0 Pin T0C T 0 T0C T 1 THn 8 bits Interrupt T0 Pin Control Toggle ENT0 AUXR1...

Page 49: ... bit ENT0 in the AUXR1 register The port output will be a logic 1 prior to the first timer overflow when this mode is turned on In order for this mode to function the T0C T bit must be cleared selecting PCLK as the clock source for the timer TL0 8 bits TR0 T0 Pin C T 0 C T 1 Interrupt T0 Pin Control Toggle ENT0 TF0 PCLK Overflow TH0 8 bits Interrupt Control TF1 Overflow TR1 PCLK T0 Pin functions a...

Page 50: ...Philips Semiconductors User s Manual Preliminary P89LPC901 902 903 TIMERS 0 AND 1 2003 Dec 8 50 ...

Page 51: ...he RTC RTCCON Real time clock control RTCH Real time clock counter reload high bits 22 15 RTCL Real time clock counter reload low bits 14 7 The Real time clock system timer can be enabled by setting the RTCEN RTCCON 0 bit The Real time clock is a 23 bit down counter initialized to all 0 s when RTCEN 0 that is comprised of a 7 bit prescaler and a 16 bit loadable down counter When RTCEN is written w...

Page 52: ...crystal DIVM Medium frequency crystal XCLK 01 10 11 Medium frequency crystal DIVM CCLK 0 1 0 00 Low frequency crystal DIVM Low frequency crystal XCLK 01 10 11 Low frequency crystal DIVM CCLK 0 1 1 00 RC Oscillator DIVM High frequency crystal XCLK 01 Medium frequency crystal XCLK 10 Low frequency crystal XCLK 11 RC Oscillator DIVM CCLK 1 0 0 00 WDT Oscillator DIVM High frequency crystal XCLK 01 Med...

Page 53: ...Wake Up If ERTC RTCCON 1 EWDRT IEN0 6 and EA IEN0 7 are set to 1 RTCF can be used as an interrupt source This interrupt vector is shared with the watchdog timer It can also be a source to wake up the device Reset Sources Affecting the Real time Clock Only power on reset will reset the Real time Clock and its associated SFRs to their default state FOSC2 UCFG1 2 FOSC1 UCFG1 1 FOSC0 UCFG1 0 RTCS1 0 C...

Page 54: ...ed for future use Should not be set to 1 by user programs RTCCON 1 ERTC Real time Clock interrupt enable The Real time clock shares the same interrupt as the watchdog timer Note that if the user configuration bit WDTE UCFG1 7 is 0 the watchdog timer can be enabled to generate an interrupt Users can read the RTCF RTCCON 7 bit to determine whether the Real time clock caused the interrupt RTCCON 0 RT...

Page 55: ...ode If PMOD1 0 11 the circuitry for the Brownout Detection is disabled for lowest power consumption BOPD defaults to 0 indicating brownout detection is enabled on power on if BOE is programmed If Brownout Detection is enabled the operating voltage range for VDD is 2 7V 3 6V and the brownout condition occurs when VDD falls below the Brownout trip voltage VBO see D C Electrical Characteristics and i...

Page 56: ...s 2 4V 3 6V 1 programmed 11 total power down X X X X 11 any mode other than total power down 1 brownout detect powered down X X X Brownout disabled VDD operating range is 2 4V 3 6V However BOPD is default to 0 upon power up 0 brownout detect active 0 brownout detect generates reset X X Brownout reset enabled VDD operating range is 2 7V 3 6V Upon a brownout reset BOF RSTSRC 5 will be set to indicat...

Page 57: ...own mode it will start the oscillator immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 1024 CPU clocks after start up when one of the crystal oscillator configurations is used or 256 clocks after start up for the internal RC or external clock input configurations Some chip functions continue to operate and draw power during Power down mod...

Page 58: ... FE for the UART This bit also determines the location of the UART receiver interrupt RI see description on RI in Figure 8 3 PCON 5 BOPD Brownout Detect Power down When 1 Brownout Detect is powered down and therefore disabled When 0 Brownout Detect is enabled Note BOPD must be 0 before any programming or erasing commands can be issued Otherwise these commands will be aborted PCON 4 BOI Brownout De...

Page 59: ...d for future use PCONA 5 VCPD Analog Voltage Comparator Power down When 1 the voltage comparator is powered down User must disable the voltage comparator prior to setting this bit PCONA 4 Not used Reserved for future use PCONA 3 Not used Reserved for future use PCONA 2 Not used Reserved for future use PCONA 1 SPD Serial Port UART Power down When 1 the internal clock to the UART is disabled Note th...

Page 60: ...Philips Semiconductors User s Manual Preliminary P89LPC901 902 903 POWER MONITORING FUNCTIONS 2003 Dec 8 60 ...

Page 61: ...d rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Baud Rate Generator and Selection section Mode 2 11 bits are transmitted through TxD or received through RxD start bit logical 0 8 data bits LSB first a programmable 9th data bit and a stop bit logical 1 When data is transmitted the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for ex...

Page 62: ...ud Rate Generator is disabled the BRGEN bit in the BRGCON register is 0 This avoids the loading of an interim value to the baud rate generator CAUTION If either BRGR0 or BRGR1 is written when BRGEN 1 the result is unpredictable Table 8 2 Baud Rate Generation for UART Register Description SFR Location PCON Power Control 87H SCON Serial Port UART Control 98H SBUF Serial Port UART Data Buffer 99H SAD...

Page 63: ...break condition has been detected the UART will go into an idle state and remain in this idle state until a stop bit has been received The break detect can be used to reset the device by setting the EBRR bit AUXR1 6 A break detect reset will force the high byte of the program counter to be equal to the Boot Vector contents and the low byte cleared to 00h The first instruction will be fetched from ...

Page 64: ...ables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then Rl will not be activated if the received 9th data bit RB8 is 0 In Mode 0 SM2 should be 0 In Mode 1 SM2 must be 0 SCON 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception SCON 3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3 Set...

Page 65: ...ls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to SBUF and there is also one more transmit interrupt generated at the beginning INTLO 0 or the end INTLO 1 of the STOP bit of the last character sent i e no more data in buffer This last interrupt can be used to indicate that all transmit operations...

Page 66: ... start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is lost ...

Page 67: ...tected when 11 consecutive bits are sensed low and is reported in the status register SSTAT For Mode 1 this consists of the start bit 8 data bits and two stop bit times For Modes 2 3 this consists of the start bit 9 data bits and one stop bit The break detect bit is cleared in software or by a reset The break detect can be used to reset the device This occurs if the UART is enabled and the the EBR...

Page 68: ...data The following occurs during a transmission assuming eight data bits 1 The double buffer is empty initially 2 The CPU writes to SBUF 3 The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately 4 If there is more data go to 6 else continue on 5 5 If there is no more data then If DBISEL is 0 no more interrupts will occur If DBISEL is 1 and INTLO is 0 a Tx interrup...

Page 69: ...es 1 2 and 3 becomes as follows 1 The double buffer is empty initially 2 The CPU writes to TB8 3 The CPU writes to SBUF 4 The SBUF TB8 data is loaded to the shift register and a Tx interrupt is generated immediately 5 If there is more data go to 7 else continue on 6 6 If there is no more data then If DBISEL is 0 no more interrupt will occur If DBISEL is 1 and INTLO is 0 a Tx interrupt will occur a...

Page 70: ...eive the data bytes that follow The slaves that weren t being addressed leave their SM2 bits set and go on about their business ignoring the subsequent data bytes Note that SM2 has no effect in Mode 0 and must be 0 in Mode 1 Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to mak...

Page 71: ...s in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address fo...

Page 72: ...Philips Semiconductors User s Manual Preliminary P89LPC901 902 903 UART P89LPC903 2003 Dec 8 72 ...

Page 73: ...ut Detect Watchdog Timer Software reset UART break character detect reset P89LPC903 For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a 0 to the corresponding bit More than one flag bit may be set During a power on reset both POF and BOF are set but the ...

Page 74: ...wer up condition The POF flag will remain set until cleared by software by writing a 0 to the bit Note On a Power on reset both BOF and this bit will be set while the other flag bits are cleared RSTSRC 3 R_BK Break detect reset If a break detect occurs and EBRR AUXR1 6 is set to 1 a system reset will occur This bit is set to indicate that the system reset is caused by a break detect Cleared by sof...

Page 75: ...mmediate interrupt service Comparator Configuration The comparator s have a control register s CMPn and is shown in Figure 10 1 The possible configurations for the comparator are shown in Figure 10 5 Figure 10 1 Comparator Control Registers CMP1 and CMP2 CMPn Address ACh Not bit addressable Reset Source s Any reset Reset Value xx000000B BIT SYMBOL FUNCTION CMP 7 6 Reserved for future use CMP 5 CEn...

Page 76: ... and Output Connections P89LPC901 Figure 10 3 Comparator Input and Output Connections P89LPC902 CIN1A Comparator P0 5 CMPREF Vref CN1 Change Detect CMF1 Interrupt EC CO1 P0 4 CIN1A Comparator 1 CO1 OE1 P0 5 CMPREF Vref P0 2 CIN2A Comparator 2 CO2 OE2 CN1 CMP2 P0 0 CMP1 P0 6 Change Detect CMF1 Change Detect CMF2 Interrupt CN2 EC ...

Page 77: ...e The flag may be polled by software or may be used to generate an interrupt The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IEN0 register When a comparator is disabled the comparator s output COx goes high If the comparator output was low and then is disabled the resulting transition of the comp...

Page 78: ...es power in Power down and Idle modes as well as in the normal operating mode This fact should be taken into account when system power consumption is an issue To minimize power consumption the user can disable the comparator via PCONA 5 or put the device in Total Power down mode Comparator Configuration Example The code shown below is an example of initializing the comparator This comparator is co...

Page 79: ... Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in the 87LPC76x series the user needs to set KBPATN 0FFH and PATN_SEL 0 not equal then any key connected to Port0 which is enabled by KBMASK register will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be ...

Page 80: ... Pattern in KBPATN to generate the interrupt When clear Port 0 has to be not equal to the value of KBPATN register to generate the interrupt KBCON 0 KBIF Keypad Interrupt Flag Set when Port 0 matches user defined conditions specified in KBPATN KBMASK and PATN_SEL Needs to be cleared by software by writing 0 7 6 5 4 3 2 1 0 PATN_SEL KBIF KBMASK Address 86h Not bit addressable Reset Source s Any res...

Page 81: ...use of a Keypad Interrupt Note the Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective Bit positions KBMASK 7 KBMASK 3 and KBMASK 1 should always be written as a 0 7 6 5 4 3 2 1 0 KBMASK 6 KBMASK 5 KBMASK 4 KBMASK 2 KBMASK 0 KBMASK Address 86h Not bit addressable Reset Source s Any reset Reset Value 00000000B BIT SYMBOL FUNCTION KBMASK 7 6 Reserved KBM...

Page 82: ...Philips Semiconductors User s Manual Preliminary P89LPC901 902 903 KEYPAD INTERRUPT KBI 2003 Dec 8 82 ...

Page 83: ...along with WDTE is designed to force certain operating conditions at power up Refer to the Table for details Table 12 1 Watchdog timer configuration Figure 12 3 shows the watchdog timer in watchdog mode It consists of a programmable 13 bit prescaler and an 8 bit down counter The down counter is clocked decremented by a tap taken from the prescaler The clock source for the prescaler is either PCLK ...

Page 84: ...V WFEED1 0A5h do watchdog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt This sequence assumes that the P89LPC901 902 903 interrupt system is enabled and there is a possibility of an interrupt request occuring during the feed sequence If an interrupt was allowed to be serviced and the service routine contained any SFR writes it would trigger a watchdog reset If it is ...

Page 85: ...ressable Reset Source s See reset value below Reset Value 111xx1 1B Note WDCON 7 6 5 2 0 set to 1 any reset WDCON 1 cleared to 0 on Power on reset set to 1 on watchdog reset not affected by any other reset BIT SYMBOL FUNCTION WDCON 7 5 PRE2 PRE0 Clock Prescaler Tap Select Refer to Table for details WDCON 4 3 Reserved for future use Should not be set to 1 by user program WDCON 2 WDRUN Watchdog Run ...

Page 86: ...85 41 0ms 2 73ms 010 0 129 322 5µs 21 5µs 255 32 769 81 9ms 5 46ms 011 0 257 642 5µs 42 8µs 255 65 537 163 8ms 10 9ms 100 0 513 1 28ms 85 5µs 255 131 073 327 7ms 21 8ms 101 0 1 025 2 56ms 170 8µs 255 262 145 655 4ms 43 7ms 110 0 2 049 5 12ms 341 5µs 255 524 289 1 31s 87 4ms 111 0 4097 10 2ms 682 8µs 255 1 048 577 2 62s 174 8ms 8 Bit Down Counter MOV WFEED1 0A5H MOV WFEED2 05AH WDL C1H PRE2 PRE1 PR...

Page 87: ...hdog Clock Source below Power down mode will also prevent PCLK from running and therefore the watchdog is effectively disabled Watchdog Clock Source The watchdog timer system has an on chip 400KHz oscillator The watchdog timer can be clocked from either the watchdog oscillator or from PCLK refer to Figure 12 1 by configuring the WDCLK bit in the Watchdog Control Register WDCON When the watchdog fe...

Page 88: ... watchdog may become disabled when the old clock source is disabled For example suppose PCLK WCLK 0 is the current clock source After WCLK is set to 1 the program should wait at least two PCLK cycles 4 CCLKs after the feed completes before going into Power down mode Otherwise the watchdog could become disabled when CCLK turns off The watchdog oscillator will never become selected as the clock sour...

Page 89: ...required in order to have a periodic wakeup is determined by the power consumption of the internal oscillator source used to produce the wakeup The Real time clock running from the internal RC oscillator can be used The power consumption of this oscillator is approximately 300uA Instead if the WDT is used to generate interrupts the current is reduced to approximately 50uA Whenever the WDT underflo...

Page 90: ...Philips Semiconductors User s Manual Preliminary P89LPC901 902 903 WATCHDOG TIMER 2003 Dec 8 90 ...

Page 91: ...s the DPS bit is toggled Specific instructions affected by the Data Pointer selection are INC DPTR Increments the Data Pointer by 1 JMP A DPTR Jump indirect relative to DPTR value AUXR1 Address A2h Not bit addressable Reset Source s Any reset Reset Value 000000x0B BIT SYMBOL FUNCTION AUXR1 7 CLKLP Clock Low Power Select When set reduces power consumption in the clock circuits Can be used when the ...

Page 92: ... that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC901 902 903 since the part does not have an external data bus However they may be used to access Flash configuration information see Flash Configuration section Bit 2 of AUXR1 is permanently wired as a...

Page 93: ... elements These include UCFG1 the Boot Vector Status Bit security bytes and signature bytes Access of these elements uses a slightly different method than that used to access the user code memory Using Flash as data storage IAP Lite provides an erase program function that makes it easy for one or more bytes within a page to be erased and pro grammed in a single operation without the need to erase ...

Page 94: ...n was aborted the user s code will need to repeat the process starting with loading the page register The erase program cycle takes 4ms to complete regardless of the number of bytes that were loaded into the page register Erasing programming of a single byte or multiple bytes in code memory is accomplished using the following steps Write the LOAD command 00H to FMCON The LOAD command will clear al...

Page 95: ...ogram erase or CRC a secured sector or page FMCON 0 OI Operation interrupted Set when cycle aborted due to an interrupt or reset 7 6 5 4 3 2 1 0 HVA HVE SV OI Inputs R3 number of bytes to program byte R4 page address MSB byte R5 page address LSB byte R7 pointer to data buffer in RAM byte Outputs R7 status byte C clear on no error set on error LOAD EQU 00H EP EQU 68H PGM_USER MOV FMCON LOAD load co...

Page 96: ...e status register When written this is a command register Note that the status bits are cleared to 0 s when the command is written FMDATA Flash Data Register Accepts data to be loaded into or from the flash element FMADRL Flash memory address low Used to specify the flash element The flash elements that may be accessed and their addresses are shown in Table 14 1 unsigned char idata dbytes 16 data ...

Page 97: ...s during erasing programming the user code should check the OI flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user s code will need to repeat the process Reading additional flash elements The read cycle is accomplished using the following steps Write the address of the flash element to FMADRL Write the CONF command 6CH to FM...

Page 98: ... for return MOV A R7 read status ANL A 0FH save only four lower bits JNZ BAD see if good or bad CLR C clear error flag if good RET and return BAD SETB C set error flag if bad RET and return unsigned char Fm_stat status result bit PGM_EL unsigned char unsigned char bit prog_fail void main prog_fail PGM_EL 0x02 0x1C bit PGM_EL unsigned char el_addr unsigned char el_data define CONF 0x6C access flash...

Page 99: ...t by the program after start of execution These features are configured through the use of Flash byte UCFG1 shown in Figure 14 7 include REG921 H unsigned char READ_EL unsigned char unsigned char GET_EL void main GET_EL READ_EL 0x02 unsigned char READ_EL unsigned char el_addr define CONF 0x6C access flash elements unsigned char el_data local for element data FMADRL el_addr write element address to...

Page 100: ...ction Brownout Detection UCFG1 4 WDSE Watchdog Safety Enable bit Refer to Table for details UCFG1 3 Reserved should remain unprogrammed at zero UCFG1 2 0 FOSC2 FSOC0 CPU oscillator type select See section Low Power Select P89LPC901 for additional information Combinations other than those shown below should not be used They are reserved for future use When FOSC2 0 select either the internal RC or W...

Page 101: ...obal erase are allowed 1 x x Security violation flag set for program or erase commands Cycle aborted Memory contents unchanged Global erase is allowed SECx Address xxxxh Unprogrammed value 00h BIT SYMBOL FUNCTION SECx 7 3 Reserved should remain unprogrammed at zero SECx 2 EDISx Erase Disable x Disables the ability to perform an erase of sector x in IAP mode When programmed this bit and sector x ca...

Page 102: ...start execution at an address comprised of 00H in the lower eight bits and this BOOTVEC as the upper bits after a reset See section Power On reset code execution on page 73 7 6 5 4 3 2 1 0 BOOTV4 BOOTV3 BOOTV2 BOOTV1 BOOTV0 BOOTSTAT Address xxxxh Factory default value 00h BIT SYMBOL FUNCTION BOOTSTAT 7 1 Reserved should remain unprogrammed at zero BOOTSTAT 0 BSB Boot Status Bit If programmed to 1 ...

Page 103: ...egister from A with borrow 1 1 98 9F SUBB A dir Subtract direct byte from A with borrow 2 1 95 SUBB A Ri Subtract indirect memory from A with borrow 1 1 96 97 SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 07 DEC A Decrement A 1 1 14 DEC Rn Decrement r...

Page 104: ... direct byte 2 1 62 XRL dir data Exclusive OR immediate to direct byte 3 2 63 CLR A Clear A 1 1 E4 CPL A Complement A 1 1 F4 SWAP A Swap Nibbles of A 1 1 C4 RL A Rotate A left 1 1 23 RLC A Rotate A left through carry 1 1 33 RR A Rotate A right 1 1 03 RRC A Rotate A right through carry 1 1 13 DATA TRANSFER MOV A Rn Move register to A 1 1 E8 EF MOV A dir Move direct byte to A 2 1 E5 MOV A Ri Move in...

Page 105: ...ta A16 1 2 F0 PUSH dir Push direct byte onto stack 2 2 C0 POP dir Pop direct byte from stack 2 2 D0 XCH A Rn Exchange A and register 1 1 C8 CF XCH A dir Exchange A and direct byte 2 1 C5 XCH A Ri Exchange A and indirect memory 1 1 C6 C7 XCHD A Ri Exchange A and indirect memory nibble 1 1 D6 D7 BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 ...

Page 106: ...bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 10 JMP A DPTR Jump indirect relative DPTR 1 2 73 JZ rel Jump on accumulator 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relat...

Page 107: ...ation that disabling comparator could cause an interrupt if comparator output was low when disabled and compar ator interrupt is enabled Added inforamtion regarding VPOR specifications Changed KBI on interrupt figure to KBIF New WDT description replaces previous to correct technical information Added comment regarding direction of RC oscillator change when changing TRIM value Added information reg...

Page 108: ...Philips Semiconductors User s Manual Preliminary P89LPC901 902 903 REVISION HISTORY 2003 Dec 8 108 ...

Page 109: ...nce voltage 83 interrupt 77 power reduction modes 78 Analog comparators and power reduction 41 B Block diagram 9 BRGCON writing to 24 Brownout detection 55 enabling and disabling 55 operating range 55 options 56 rise and fall times of Vdd 55 C CLKLP 33 Clock CPU clock 27 CPU divider DIVM 32 definitions 27 external input option 29 PCLK 27 RCCLK 27 wakeup delay 32 Clock output 28 D Data EEPROM ...

Page 110: ... 45 51 55 61 73 75 79 83 91 93 103 107 Boot Status 102 Boot Vector 102 features 93 hardware activation of the boot loader 73 power on reset code execution 73 I IAP programming 93 Interrupts 39 arbitration ranking 35 external input pin glitch suppression 37 external inputs 36 keypad 37 priority structure 35 wake up from power down 37 Interrutps edge triggered 37 ISP programming 93 K Keypad interrup...

Page 111: ...ts additional features 42 I O 39 input only configuration 41 open drain output configuration 40 Port 0 analog functions 41 Port 2 in 20 pin package 41 push pull output configuration 41 quasi bidirectional output configuration 39 Power monitoring functions 73 Power reduction modes 57 normal mode 57 power down mode partial 57 Power down mode total 57 Power on detection 56 R Real time clock 51 clock ...

Page 112: ...TAT 65 TAMOD 46 TCON 47 TMOD 45 TRIM 28 29 95 UCFG1 100 WDCON 85 SFRs undefined locations use of 16 Special Function Registers SFR table 16 19 22 T Timer counters 45 mode 0 46 mode 1 46 mode 2 8 bit auto reload 46 mode 3 seperates TL0 TH0 47 mode 6 8 bit PWM 47 toggle output 49 TRIM SFR power on reset value 24 U UART 61 automatic address recognition 70 baud rate generator 62 BRGR1 and BRGR0 updati...

Page 113: ...gister 61 mode 1 66 mode 1 8 bit variable baud rate 61 mode 2 67 mode 2 9 bit fixed baud rate 61 mode 3 67 mode 3 9 bit variable baud rate 61 multiprocessor communications 70 SFR locations 62 status register 65 transmit interrupts with double buffering enabled modes 1 2 and 3 68 W Watchdog timer 83 feed sequence 84 timer mode 87 watchdog function 83 watchdog timeout values 86 WDCLK 0 and CPU power...

Page 114: ...tems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes in th...

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